Article

Thread warping: a framework for dynamic synthesis of thread accelerators

Authors:

Frank VahidAuthors Info & Claims

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 93 - 98

https://doi.org/10.1145/1289816.1289841

Published: 30 September 2007 Publication History

Abstract

We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGA.an advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4x to 502x, averaging 130x compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11x speedup.

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Cited By

Kim CJeong SCho SLee YSong WKim YKim HLee J(2021)Thread-aware area-efficient high-level synthesis compiler for embedded devicesProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370341(327-339)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370341
Barron LAbdelrahman T(2018)User-Transparent Translation of Machine Instructions to Programmable Hardware2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2018.00013(7-14)Online publication date: May-2018
https://doi.org/10.1109/IPDPSW.2018.00013
Choi JBrown SAnderson J(2017)From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272062325:10(2867-2880)Online publication date: Oct-2017
https://doi.org/10.1109/TVLSI.2017.2720623
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Index Terms

Thread warping: a framework for dynamic synthesis of thread accelerators
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Published In

cover image ACM Conferences

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

September 2007

284 pages

ISBN:9781595938244

DOI:10.1145/1289816

General Chairs:
Soonhoi Ha
Seoul National University, Korea
,
Kiyoung Choi
Seoul National University, Korea
,
Program Chairs:
Nikil Dutt
UC Irvine, USA
,
Jürgen Teich
University of Erlangen-Nuremberg, Germany

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 September 2007

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ESWEEK07

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ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Kim CJeong SCho SLee YSong WKim YKim HLee J(2021)Thread-aware area-efficient high-level synthesis compiler for embedded devicesProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370341(327-339)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370341
Barron LAbdelrahman T(2018)User-Transparent Translation of Machine Instructions to Programmable Hardware2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2018.00013(7-14)Online publication date: May-2018
https://doi.org/10.1109/IPDPSW.2018.00013
Choi JBrown SAnderson J(2017)From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272062325:10(2867-2880)Online publication date: Oct-2017
https://doi.org/10.1109/TVLSI.2017.2720623
Choi JRuo Long Lian Brown SAnderson J(2016)A unified software approach to specify pipeline and spatial parallelism in FPGA hardware2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2016.7760775(75-82)Online publication date: Jul-2016
https://doi.org/10.1109/ASAP.2016.7760775
Rodrıguez AValverde Jde la Torre E(2015)Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393297(1-7)Online publication date: Dec-2015
https://doi.org/10.1109/ReConFig.2015.7393297
Choi JBrown SAnderson J(2015)Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware2015 International Conference on Field Programmable Technology (FPT)10.1109/FPT.2015.7393142(152-159)Online publication date: Dec-2015
https://doi.org/10.1109/FPT.2015.7393142
Yan LWu BWen YZhang SChen T(2014)A reconfigurable processor architecture combining multi-core and reconfigurable processing unitsTelecommunications Systems10.1007/s11235-013-9791-155:3(333-344)Online publication date: 1-Mar-2014
https://dl.acm.org/doi/10.1007/s11235-013-9791-1
Choi JBrown SAnderson J(2013)From software threads to parallel hardware in high-level synthesis for FPGAs2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718365(270-277)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718365
Bauer LGrudnitsky AShafique MHenkel J(2012)PATSProceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2012.43(208-215)Online publication date: 29-Apr-2012
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Rutzig M(2012)Multicore Platforms: Processors, Communication and MemoriesAdaptable Embedded Systems10.1007/978-1-4614-1746-0_8(243-277)Online publication date: 20-Oct-2012
https://doi.org/10.1007/978-1-4614-1746-0_8
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