EBDN: Entropy-Based Double Nonuniform Sensing Algorithm for LDPC Decoding in TLC nand Flash Memory
Pages 1914 - 1918
Abstract
Low-density parity-check (LDPC) codes are widely employed in NAND flash memory to improve the reliability of data. However, LDPC has serious latency problems when the raw bit error rate (RBER) is high. The reason is that not only a sufficient sensing level is required to obtain accurate soft information but also a high number of iterations are needed. To reduce the latency of LDPC, an entropy-based double nonuniform (EBDN) sensing algorithm is proposed in this article. The basic idea of this algorithm is to exploit the entropy to quantify the nonuniformity of intrastate and interstate. And the sensing levels are placed in a targeted manner based on the entropy, thereby significantly reducing the number of sensing levels without reducing the LDPC error correction performance. The experimental results show that the proposed algorithm can decrease the number of iterations of LDPC by approximately 70% and reduce the read latency by 34.52% compared with the traditional nonuniform sensing algorithm.
References
[1]
W. Liu, J. Rho, and W. Sung, “Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories,” in Proc. IEEE Workshop Signal Process. Syst. Design Implement. 2006, pp. 303–308.
[2]
F. Wuet al., “Using error modes aware LDPC to improve decoding performance of 3-D TLC NAND flash,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 39, no. 4, pp. 909–921, Apr. 2020.
[3]
Y. Yeh, A. Fazeli, and P. H. Siegel, “Optimal placement of read thresholds for coded NAND flash memory,” in Proc. IEEE Int. Conf. Commun., 2021, pp. 1–7.
[4]
G. Dong, N. Xie, and T. Zhang, “On the use of soft-decision error-correction codes in NAND flash memory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 2, pp. 429–439, Feb. 2011.
[5]
S. Qi, D. Feng, and J. Liu, “Optimal voltage signal sensing of NAND flash memmory for LDPC code,” in Proc. IEEE Workshop Signal Process. Syst. (SiPS), 2014, pp. 1–6.
[6]
C. A. Aslam, Y. L. Guan, and K. Cai, “Read and write voltage signal optimization for multi-level-cell (MLC) NAND flash memory,” IEEE Trans. Commun., vol. 64, no. 4, pp. 1613–1623, Apr. 2016.
[7]
X. Lin, G. Han, S. Ouyang, Y. Li, and Y. Fang, “Low-complexity detection and decoding scheme for LDPC-coded MLC NAND flash memory,” China Commun., vol. 15, no. 6, pp. 58–67, Jun. 2018.
[8]
Q. Li, L. Shi, Y. Cui, and C. J. Xue, “Exploiting asymmetric errors for LDPC decoding optimization on 3D NAND flash memory,” IEEE Trans. Comput., vol. 69, no. 4, pp. 475–488, Apr. 2020.
[9]
D. Wei, Z. Piao, H. Feng, L. Qiao, C. Hu, and X. Peng, “TCSE: A target cell states elimination coding strategy for highly reliable data storage based on 3-D NAND flash memory,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 41, no. 12, pp. 5299–5312, Dec. 2022.
[10]
Y. Du, Y. Gao, S. Huang, and Q. Li, “LDPC level prediction towards read performance of high-density flash memories,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 42, no. 10, pp. 3264–3274, Oct. 2023.
[11]
D. Wei, Y. Gong, L. Qiao, and L. Deng, “A hardware-software co-design experiments platform for NAND flash based on Zynq,” in Proc. IEEE 20th Int. Conf. Embedded Real-Time Comput. Syst. Appl., 2014, pp. 1–7.
[12]
Y. Du, D. Zou, L. Qiao, S. Liang, and C. J. Xue, “LaLDPC: Latency-aware LDPC for read performance improvement of solid state drives,” in Proc. 33rd Int. Conf. Massive Storage Syst. Technol. (MSST), 2017, pp. 1–11.
[13]
R. S. Liu, M. Y. Chuang, C. L. Yang, C. H. Li, K. C. Ho, and H. P. Li, “Improving read performance of NAND flash SSDs by exploiting error locality,” IEEE Trans. Comput., vol. 65, no. 4, pp. 1090–1102, Apr. 2016.
[14]
Q. Liet al., “Optimal read voltages decision scheme eliminating read retry operations for 3D NAND flash memories,” Microelectron. Rel., vol. 131, Apr. 2022, Art. no.
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Published: 08 January 2024
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