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10.1109/HPCC.2012.163guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Optimizing Private Memory Performance by Dynamically Deactivating Cache Coherence

Published: 25 June 2012 Publication History

Abstract

User Program has significant percentage of memory requests that target only private data, which does not need to resolve cache coherence conflicts. Yet traditional coherence protocol does not distinguish between shared and private blocks, which leaves much optimization space for memory reference latency and power consumption. This paper proposes an optimized cache coherence protocol, called PMESI, which dynamically deactivates cache coherence maintenance for private memory space. PMESI achieves two distinguishing features: the reduction of memory access latency and system power consumption. Simulation results on the cycle accurate simulator for wide range of industry benchmarks show that 54\% memory references can be efficiently optimized and program execution time is reduced 9\% on average.
  1. Optimizing Private Memory Performance by Dynamically Deactivating Cache Coherence

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    Published In

    cover image Guide Proceedings
    HPCC '12: Proceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems
    June 2012
    1821 pages
    ISBN:9780769547497

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    IEEE Computer Society

    United States

    Publication History

    Published: 25 June 2012

    Author Tags

    1. PMESI protocol
    2. directory coherence protocol
    3. operating system
    4. private memory space

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