A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Authors: 
Alberto A. Del Barrio, Seda Ogrenci Memik, MaríA C. Molina, José M. MendíAs, RomáN HermidaAuthors Info & Claims
Alberto A. Del Barrio, Seda Ogrenci Memik, MaríA C. Molina, José M. MendíAs, RomáN HermidaAuthors Info & ClaimsPages 119 - 130
Abstract
State of the art multi-objective synthesis flows use to degrade some parameters of the circuit while trying to optimize the target one. This paper addresses the power reduction problem in heterogeneous datapaths, while keeping a similar area and execution time with respect to the baseline case. Our specific approach first diminishes the area via fragmentation techniques and afterwards it gives it back with the introduction of Low Power Functional Units (LP-FUs) that occupy more area than their corresponding non-low power counterparts. Furthermore, a fragmentation algorithm more suitable for power reduction is proposed. Results show that it is possible to diminish power by 27% on average (49% in the best case).
References
[1]
Coussy, P. and Morawiec, A., High-Level Synthesis. From Algorithm to Digital Circuit. 2008. 1st ed. Springer, Netherlands.
[2]
Mohanty, S., Ranganathan, N., Kougianos, E. and Patra, P., Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. 2008. 1st ed. Springer.
[3]
V. Kursun, E.G. Friedman, Low swing dual threshold voltage domino logic, in: Proceedings of the 12th ACM Great Lakes Symposium on VLSI, 2002, pp. 47-52.
[4]
A. Keshavarzi, S. Narendra, S. Borkar, C. Hawkins, K. Roy, V. De, Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's, in: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, pp. 252-254.
[5]
K.-C. Kuo, C-W. Chou. Low power multiplier with bypassing and tree structure, in: Proceedings of the 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006, pp. 602-605.
[6]
Wang, C.-C. and Sung, G.-N., Low-power multiplier design using a bypassing technique. Journal of Signal Processing Systems. v57 i3. 331-338.
[7]
G. Economakos, K. Anagnostopoulos, Bit level architectural exploration technique for the design of low power multipliers, in: Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, 2006, pp. 1483-1486.
[8]
Wen, M.-C., Wang, S.-J. and Lin, Y.-N., Low-power parallel multiplier with column bypassing. Electronic Letters. v41 i10. 581-583.
[9]
M. Nickray, M. Dehyadgari, A. Sobhani, A. Afzalikusha, Multiplier for correlative input patterns, in: The 17th International Conference on Microelectronics, 2005, pp. 72-74.
[10]
Navarro-Botello, V., Montiel-Nelson, J.A. and Nooshabadi, S., High performance low power CMOS dynamic logic for arithmetic circuits. Microelectronics Journal. v38 i4-5. 482-488.
[11]
E. Musoll, J. Cortadella, High-level synthesis techniques for reducing the activity of functional units, in: Proceedings of the 1995 International Symposium on Low Power Design, 1995, pp. 99-104.
[12]
W. Wang, T.K. Tan, J. Luo, Y. Fei, L. Shang, K.S. Vallerio, L. Zhong, A. Raghunathan, N.K. Jha, A comprehensive HLS system for control-flow intensive behaviors, in: Proceedings of the 13th ACM Great Lakes Symposium on VLSI, 2003, pp. 11-14.
[13]
M.A. Ochoa-Montiel, B.M. Al-Hashimi, P. Kollig, Exploiting power-area tradeoffs in behavioural synthesis through clock and operations throughput selection, in: Proceedings of the 2007 Asia and South Pacific Design Automation Conference, 2007, pp. 517-522.
[14]
M. Mukherjee, R. Vemuri, A novel synthesis strategy driven by partial evaluation based circuit reduction for application specific DSP circuits, in: Proceedings of the 21st International Conference on Computer Design, 2003, pp. 436-440.
[15]
G. Caffarena, J.A. Lopez, C. Carreras, O. Nieto-Taladriz, High-level synthesis of multiplier word-length DSP algorithms using heterogeneous-resource FPGAs, in: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications, 2006, pp. 675-678.
[16]
A.A. Del Barrio, M.C. Molina, J.M. Mendias, E. Andres, R. Hermida, Restricted chaining and fragmentation techniques in power aware high level synthesis, in: Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2008, pp. 267-273.
[17]
Molina, M.C., Mendias, J.M. and Hermida, R., Behavioural specification allocation to minimize bit level waste of functional units. IEE Proceedings of Computers and Digital Techniques. v150 i5. 321-329.
[18]
Molina, M.C., Ruiz-Sautua, R., Mendias, J.M. and Hermida, R., Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Transactions on CAD of Integrated Circuits and Systems. v25 i1. 31-46.
[19]
H.-C. Yang, L.-R. Dung, On multiple-voltage high-level synthesis using algorithmic transformations, in: Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, pp. 872-876.
[20]
Mohanty, S.P. and Ranganathan, N., Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Transactions on Design Automation of Electronic Systems. v10 i2. 330-353.
[21]
Benini, L., Bogliolo, A. and De Micheli, G., A Survey of Design Techniques for System-level Dynamic Power Management, Readings in Hardware/Software Co-design. 2002. Kluwer Academic Publishers.
[22]
Koren, I., Computer Arithmetic Algorithms. 2002. 2nd ed. A.K. Peters.
[23]
Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Transactions on CAD of Integrated Circuits and Systems. v8 i6. 661-679.
[24]
Brassard, G. and Bratley, P., Fundamentals of Algorithmics. 1996. 1st ed. Prentice Hall.
[25]
Devadas, S. and Newton, A.R., Algorithms for hardware allocation in data path synthesis. IEEE Transactions on CAD of Integrated Circuits and Systems. v8 i7. 768-781.
[26]
J. Choi, J. Jeon, K. Choi, Power minimization of functional units partially guarded computation, in: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, pp. 131-136.
[27]
Zhong, L. and Jha, N.K., Interconnect-aware low-power high-level synthesis. IEEE Transactions on CAD of Integrated Circuits and Systems. v24 i3. 336-351.
[28]
D.S.H. Ram, M.C. Bhuvaneswari, S.M. Logesh, A novel evolutionary technique for multi-objective power, area and delay optimization in high level synthesis of datapaths, in: IEEE Computer Society Annual Symposium on VLSI, 2011, pp. 290-295.
[29]
S.M. Logesh, D.S.H. Ram, M.C. Bhuvaneswari, Multi-objective optimization of power, area and delay during high-level synthesis of DFG's-a genetic algorithm approach, in: International Conference on Electronics Computer Technology, 2011, pp. 108-112.
[30]
Navi, K., Maeen, M., Foroutan, V., Timarchi, S. and Kavehei, O., A novel low-power full-adder cell for low voltage. Integration, The VLSI Journal. v42 i4. 457-467.
[31]
A.A. Del Barrio, S. Ogrenci Memik, M.C. Molina, J.M. Mendias, R. Hermida, Power optimization in heterogenous datapaths, in: Design, Automation and Test in Europe, 2011, pp. 1400-1405.
Recommendations
Interconnect-aware low-power high-level synthesis
Interconnects (wires, buffers, clock distribution networks, multiplexers, and busses) consume a significant fraction of total circuit power. In this paper, we demonstrate the importance of optimizing on-chip interconnects for power during high-level ...
Register allocation for high-level synthesis using dual supply voltages
DAC '09: Proceedings of the 46th Annual Design Automation ConferenceReducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the ...
Scheduling and resource binding for low power
ISSS '95: Proceedings of the 8th international symposium on System synthesisAbstract: Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-...
Comments
Information & Contributors
Information
Published In
Copyright © Elsevier B.V. © 2012.
Publisher
Elsevier Science Publishers B. V.
Netherlands
Publication History
Published: 01 March 2013
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 27 Dec 2024