High-level synthesis techniques for functional test pattern execution

High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow ...

The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This ...

In this study, we present a high-level testability analysis technique that evaluates the testability of a design based on the proposed controllability and observability measures. The control-data flow graph (CDFG) constructed from the VHDL description of a ...