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View all- Tunali OAltun M(2017)A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar ArraysACM Computing Surveys10.1145/312564150:6(1-35)Online publication date: 14-Nov-2017
Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures
Pages 959 - 967
Abstract
Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation- and defect-aware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement.
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Published: 01 September 2016
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View all- Tunali OAltun M(2017)A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar ArraysACM Computing Surveys10.1145/312564150:6(1-35)Online publication date: 14-Nov-2017