AUTSEG: Automatic Test Set Generator for Embedded Reactive Systems
Pages 97 - 112
Abstract
One of the biggest challenges in hardware and software design is to ensure that a system is error-free. Small errors in reactive embedded systems can have disastrous and costly consequences for a project. Preventing such errors by identifying the most probable cases of erratic system behavior is quite challenging. In this paper, we introduce an automatic test set generator called AUTSEG. Its input is a generic model of the target system, generated using the synchronous approach. Our tool finds the optimal preconditions for restricting the state space of the model. It only works locally on significant subspaces. Our approach exhibits a simpler and efficient quasi-flattening algorithm than existing techniques and a useful compiled form to check security properties and reduce the combinatorial explosion problem of state space. To illustrate our approach, AUTSEG was applied to the case of a transportation contactless card.
References
[1]
Bryant, R.E.: Graph-based algorithms for boolean function manipulation. IEEE Transaction on ComputersäC-35(8), 677—691 (1986)
[2]
Seljimi, B., Parissis, I.: Automatic generation of test data generators for synchronous programs: Lutess v2. In: Workshop on Domain Specific Approaches to Software Test Automation: in conjunction with the 6th ESEC/FSE Joint Meeting, DOSTA 2007, pp. 8—12. ACM Press, New York (2007)
[3]
DuBousquet, L., Zuanon, N.: An overview of lutess: A specification-based tool for testing synchronous software. In: ASE, pp. 208—215 (1999)
[4]
Blanc, B., Junke, C., Marre, B., Le Gall, P., Andrieu, O.: Handling state-machines specifications with gatel. Electron. Notes Theor. Comput. Sci.ä264(3), 3—17 (2010)
[5]
Calam, J.R.: Specification-Based Test Generation With TGV. CWI Technical Report SEN-R 0508, CWI (2005)
[6]
Clarke, D., Jéron, T., Rusu, V., Zinovieva, E.: STG: A symbolic test generation tool. In: Katoen, J.-P., Stevens, P. (eds.) TACAS 2002. LNCS, vol.ä2280, pp. 470—475. Springer, Heidelberg (2002)
[7]
Bentakouk, L., Poizat, P., Zaïdi, F.: A formal framework for service orchestration testing based on symbolic transition systems. In: Núñez, M., Baker, P., Merayo, M.G. (eds.) TESTCOM 2009. LNCS, vol.ä5826, pp. 16—32. Springer, Heidelberg (2009)
[8]
Xu, D.: A tool for automated test code generation from high-level petri nets. In: Kristensen, L.M., Petrucci, L. (eds.) PETRI NETS 2011. LNCS, vol.ä6709, pp. 308—317. Springer, Heidelberg (2011)
[9]
Burnim, J., Sen, K.: Heuristics for scalable dynamic test generation. In: Proceedings of the 2008 23rd IEEE/ACM International Conference on Automated Software Engineering, ASE 2008, pp. 443—446. IEEE Computer Society, Washington, DC (2008)
[10]
Li, G., Ghosh, I., Rajan, S.P.: KLOVER: A symbolic execution and automatic test generation tool for C++ programs. In: Gopalakrishnan, G., Qadeer, S. (eds.) CAV 2011. LNCS, vol.ä6806, pp. 609—615. Springer, Heidelberg (2011)
[11]
André, C.: Representation and analysis of reactive behaviors: A synchronous approach. In: Computational Engineering in Systems Applications (CESA), Lille (F), pp. 19—29. IEEE-SMC (1996)
[12]
Berry, G., Gonthier, G.: The esterel synchronous programming language: Design, semantics, implementation. Sci. Comput. Program.ä19(2), 87—152 (1992)
[13]
Paiva, A.C.R., Tillmann, N., Faria, J.C.P., Vidal, R.F.A.M.: Modeling and testing hierarchical guis. In: Proc. ASM 2005, Universite de Paris, vol.ä12, pp. 8—11 (2005)
[14]
Wasowski, A.: Flattening statecharts without explosions. SIGPLAN Not.ä39(7), 257—266 (2004)
[15]
Chiuchisan, I., Potorac, A.D.: G.A.: Finite state machine design and vhdl coding techniques. In: 10th International Conference on Development and Application Systems, Suceava, Romania, pp. 273—278. Faculty of Electrical Engineering and Computer Science (2010)
[16]
Gaffé, D.: Research web site, http://sites.unice.fr/dgaffe/recherche/research.html
[17]
Berkeley University: Berkeley logic interchange format, blif (1998)
[18]
Ressouche, A., Gaffé, D., Roy, V.: Modular compilation of a synchronous language. In: Lee, R. (ed.) Soft. Eng. Research, Management and Applications, best 17 Paper Selection of the SERA 2008 Conference, Prague, vol.ä150, pp. 157—171. Springer, Heidelberg (2008)
[19]
Chaki, S., Gurfinkel, A., Strichman, O.: Decision diagrams for linear arithmetic. In: FMCAD, pp. 53—60. IEEE (2009)
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Published: 23 September 2014
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