SIRM: Shift Insensitive Racetrack Main Memory
Authors: 
Hongbin Zhang, Bo Wei, Youyou Lu, Jiwu ShuAuthors Info & Claims
Hongbin Zhang, Bo Wei, Youyou Lu, Jiwu ShuAuthors Info & ClaimsPages 355 - 360
Abstract
Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.
References
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- SIRM: Shift Insensitive Racetrack Main Memory
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Information & Contributors
Information
Published In
Aug 2019
385 pages
ISBN:978-3-030-30708-0
DOI:10.1007/978-3-030-30709-7
© IFIP International Federation for Information Processing 2019.
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 23 August 2019
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