Article

Free access

Perturb and simplify: multi-level boolean network optimizer

Authors:

Shih-Chieh Chang,

Malgorzata Marek-SadowskaAuthors Info & Claims

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Pages 2 - 5

Published: 06 November 1994 Publication History

PDF eReader

Abstract

In this paper, we discuss the problem of optimizing a multi-level logic combinational Boolean network. Our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation ATPG based reasoning. In particular, we propose several new ways in which one or more redundant gates or wires can be added to a network. We show how to identify gates which are good candidates for local functionality change. Furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network. We also address the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests. We have performed experiments on MCNC benchmarks and compared the results to those of misII and RAMBO. Experimental results are very encouraging.

References

[1]

K.A. Bartlett et al, "Multilevel Logic Minimizing Using Implicit Don't cares," IEEE Trans. on CAD-7(6), pp. 723-740(June 1988).

Digital Library

Google Scholar

[2]

C. L. Berman and L. H. Trevillyan. "Global Flow Optimization in Automatic Logic Design," IEEE Trans. CAD 10, pp. 557-564(May 1991).

Digital Library

Google Scholar

[3]

D. Bostick et al, "The Boulder Optimal Logic Design System," Proc. ICCAD, pp. 62-65, 1987.

Google Scholar

[4]

R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, "MIS: Multi-level Interactive Logic Optimization System," IEEE Trans. on CAD, CAD-6(6), pp. 1062-1081(Nov. 1989).

Google Scholar

[5]

Shih-Chieh Chang and Malgorzata Marek-Sadowska, "Layout Driven Logic Synthesis for FPGA," Proc. Design Automation Conference. pp

Digital Library

Google Scholar

[6]

K.T. Cheng and L.A. Entrena, "Multi-Level Logic Optimization by Redundancy Addition and Removal," in Proc. European Conference On Design Automation, pp. 373-377, Feb. 1993.

Google Scholar

[7]

M.Damiani, J.C.Y.Yang and G.De Micheli, "Optimization of Combinational Logic Circuits Based on Compatible Gates", Proc. DAC'93, pp.631-636, June 1993.

Digital Library

Google Scholar

[8]

L.A. Entrena and K. T. Cheng, "Sequential Logic Optimization By Redundancy Addition and Removal", Proc. International Conference on Computer Aided Design, Nov. 1993.

Digital Library

Google Scholar

[9]

E. Detjens, G. Gannot, R. Rudell, A. L. Sangiovanni-Vincentelli and A. Wang, "Technology Mapping in MIS," Proc. ICCAD, pp. 116-119, 1987.

Google Scholar

[10]

T.Kirkand and M.R. Mercer, "A Topological Search Algorithm For ATPG," Proc. 24th Design Automation Conf., pp. 502-508, June 1987.

Digital Library

Google Scholar

[11]

C.E.Leiserson, EM.Rose, and J.B.Saxe, "Optimizing synchronous circuit by retiming", in Proc. Third Caltech Conf. on VLSI, 1983.

Google Scholar

[12]

S. Muroga et al, "The Transduction Method-Design of Logic Networks Based on Permissible Functions," IEEEE Transaction. on Computer C38(10). pp. 1404-1423 (Oct. 1989).

Digital Library

Google Scholar

[13]

M.Schulz and E.Auth, "Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques," Proc. Fault Tolerant Computing Symposium, pp. 30-34 June 1988.

Google Scholar

Cited By

View all

Saluja NGulati KKhatri S(2008)SAT-based ATPG using multilevel compatible don't-caresACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442013:2(1-18)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344420
Zhou CTang WLo WWu YLevitan S(2007)How much can logic perturbation help from netlist to final routing for FPGAsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278707(922-927)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278707
Wu YCheung CCheng DFan H(2003)Further improve circuit partitioning using GBAW logic perturbation techniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81236911:3(451-460)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.812369
Show More Cited By

Index Terms

Perturb and simplify: multi-level boolean network optimizer
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

Recommendations

Perturb and simplify: multilevel Boolean network optimizer

In this paper, we present logic optimization techniques for multilevel combinational networks. Our techniques apply a sequence of perturbations which result in simplification of the circuit. The perturbation and simplification is achieved through wires/...
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares
EDTC '96: Proceedings of the 1996 European conference on Design and Test

Earlier optimization techniques based on Automatic Test Pattern Generation could not handle external don't cares. We propose a technique that uses external don't cares during the ATPG guided logic optimization. This technique transforms external don't ...
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes part of ...

Comments

Information & Contributors

Information

Published In

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

November 1994

771 pages

ISBN:0897916905

Chairmen:
Jochen A. G. Jess
Eindhoven Univ. of Technology, Eindhoven, The Netherlands
,
Richard Rudell
Synopsys, Inc., Mountain View, CA

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 06 November 1994

Check for updates

Qualifiers

Article

Conference

ICCAD '94

Sponsor:

SIGDA
IEEE-CS

ICCAD '94: International Conference on Computer Aided Design

November 6 - 10, 1994

California, San Jose, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Upcoming Conference

ICCAD '24

Sponsor:
sigda

IEEE/ACM International Conference on Computer-Aided Design

October 27 - 31, 2024

New York , NY , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

26
Total Citations
View Citations
182
Total Downloads

Downloads (Last 12 months)23
Downloads (Last 6 weeks)8

Reflects downloads up to 14 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Saluja NGulati KKhatri S(2008)SAT-based ATPG using multilevel compatible don't-caresACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442013:2(1-18)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344420
Zhou CTang WLo WWu YLevitan S(2007)How much can logic perturbation help from netlist to final routing for FPGAsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278707(922-927)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278707
Wu YCheung CCheng DFan H(2003)Further improve circuit partitioning using GBAW logic perturbation techniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81236911:3(451-460)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.812369
Millán EEntrena LEspejo JLópez C(2003)Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniquesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2003.06.00249:12-15(529-541)Online publication date: 1-Dec-2003
https://dl.acm.org/doi/10.1016/j.sysarc.2003.06.002
San Millán EEntrena LEspejo JErnst R(2001)On the optimization power of redundancy addition and removal techniques for sequential circuitsProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603114(91-94)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603114
Veneris AAbadir MTing IGoto S(2001)Design rewiring based on diagnosis techniquesProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370516(479-484)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370516
Wohl PWaicukauski J(2000)OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNSProceedings of the 2000 IEEE International Test Conference10.5555/839295.843689Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843689
Wu YYuan XCheng DYoshida K(2000)Circuit partitioning with coupled logic restructuring techniquesProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368862(655-660)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368862
San Millán EEntrena LEspejo JChiusano SCorno F(1999)Integrating symbolic techniques in ATPG-based sequential logic optimizationProceedings of the conference on Design, automation and test in Europe10.1145/307418.307555(105-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307555
Chung KLiu CChandrakasan AKiaei S(1998)Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reductionProceedings of the 1998 international symposium on Low power electronics and design10.1145/280756.280904(215-220)Online publication date: 10-Aug-1998
https://dl.acm.org/doi/10.1145/280756.280904
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations