research-article

Device and architecture concurrent optimization for FPGA transient soft error rate

Authors:

Lei HeAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 194 - 198

Published: 05 November 2007 Publication History

Abstract

Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we show that continuous CMOS scaling dramatically increases the significance of FPGA chip-level transient soft errors in circuit elements other than configuration memory, and transient SER can no longer be ignored. We then develop an efficient, yet accurate, transient SER evaluation method, called trace based methodology, considering logic, electrical and latch-window maskings. By collecting traces on logic probability and sensitivity and re-using these traces for different device settings, we finally perform device and architecture concurrent optimization considering hundreds of device and architecture combinations. Compared to the commonly used FPGA architecture and device settings, device and architecture concurrent optimization can reduce the transient SER by 2.8X and reduce the product of energy, delay and transient SER by 1.8X.

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Cited By

Sterpone LAzimi SDu BCodinachs DGrimoldi RBehjat LHan JVelev MChen D(2017)Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060454(203-208)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060454
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Watanabe TWatanabe M(2012)Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arraysProceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications10.1007/978-3-642-28365-9_14(163-173)Online publication date: 19-Mar-2012
https://dl.acm.org/doi/10.1007/978-3-642-28365-9_14
Show More Cited By

Device and architecture concurrent optimization for FPGA transient soft error rate
1. Hardware

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Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

Publication History

Published: 05 November 2007

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Sterpone LAzimi SDu BCodinachs DGrimoldi RBehjat LHan JVelev MChen D(2017)Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060454(203-208)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060454
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Watanabe TWatanabe M(2012)Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arraysProceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications10.1007/978-3-642-28365-9_14(163-173)Online publication date: 19-Mar-2012
https://dl.acm.org/doi/10.1007/978-3-642-28365-9_14
Seto DWatanabe M(2010)MEMS dynamic optically reconfigurable gate array usable under a space radiation environmentProceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications10.1007/978-3-642-12133-3_14(134-144)Online publication date: 17-Mar-2010
https://dl.acm.org/doi/10.1007/978-3-642-12133-3_14
Feng ZHu YHe LMajumdar RRoychowdhury J(2009)IPRProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687422(105-108)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687422
Hu YFeng ZHe LMajumdar RNassif SRoychowdhury J(2008)Robust FPGA resynthesis based on fault-tolerant Boolean matchingProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509611(706-713)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509611
Cheng LLin YHe LHutton MChow P(2008)Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliabilityProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344696(159-168)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344696

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