research-article

Unified adaptivity optimization of clock and logic signals

Authors:

Shiyan Hu,

Jiang HuAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 125 - 130

Published: 05 November 2007 Publication History

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Abstract

VLSI design is increasingly sensitive to variations which often degrade the parametric yield. Post-silicon tuning techniques can compensate for specific variations on the die and thus significantly improve the yield. Previous works on adaptivity optimization for post-silicon tuning focus on either logic signal tuning or clock signal tuning. This paper proposes the first unified adaptivity optimization on logical and clock signal tuning, which enables us to significantly save resource. In addition, it does not need any assumption on variation distributions.

Our unified optimization is based on a novel linear programming formulation which can be efficiently solved by an advanced robust linear programming technique. Due to the discrete nature of the problem, the continuous solution obtained from linear programming is then efficiently discretized. This procedure involves binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation. Our experimental results demonstrate that up to 50% area cost reduction can be obtained by the unified optimization compared to optimization on logic or clock alone. In addition, the proposed discretization approach significantly outperforms the alternatives in terms of solution quality and runtime.

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Cited By

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Kim JJoo DKim T(2016)Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modesIntegration, the VLSI Journal10.1016/j.vlsi.2015.08.00552:C(91-101)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.08.005
Park KKim GKim TFettweis GNebel W(2014)Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616995(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616995
Kim JJoo DKim T(2013)An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problemProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488845(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488845
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Unified adaptivity optimization of clock and logic signals
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Published In

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

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IEEE Press

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Published: 05 November 2007

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CEDA
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IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Kim JJoo DKim T(2016)Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modesIntegration, the VLSI Journal10.1016/j.vlsi.2015.08.00552:C(91-101)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.08.005
Park KKim GKim TFettweis GNebel W(2014)Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616995(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616995
Kim JJoo DKim T(2013)An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problemProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488845(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488845
Lin KLin HHo TTsai C(2012)Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designsACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2209291.220930717:3(1-22)Online publication date: 5-Jul-2012
https://dl.acm.org/doi/10.1145/2209291.2209307
Lin KLin HHo T(2011)An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950971(825-830)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950971
Lim KKim T(2011)An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950918(503-508)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950918
Su YHon WYang CChang SChang YRoychowdhury J(2009)Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687500(535-538)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687500
Zhuo CBlaauw DSylvester DNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Variation-aware gate sizing and clustering for post-silicon optimized circuitsProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393949(105-110)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393949

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Clock skew minimization in multi-voltage mode designs using adjustable delay buffers

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