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ORCIDSébastien Pillement
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- affiliation: University of Nantes, France
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2020 – today
- 2024
[i1]Juliette Pottier, Thomas Nieddu, Bertrand Le Gal, Sébastien Pillement, Maria Méndez Real:
RISC-V processor enhanced with a dynamic micro-decoder unit. CoRR abs/2406.14999 (2024)- 2023
- [c62]Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal
, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon:
Securing a RISC-V architecture: A dynamic approach. DATE 2023: 1-5 - [c61]Quentin Dariol, Sébastien Le Nours, Domenik Helms, Ralf Stemmer, Sébastien Pillement, Kim Grüttner:
Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms. DroneSE/RAPIDO@HiPEAC 2023: 79-86 - [c60]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Divider Circuits by Hardware Reduction. SMACD 2023: 1-4 - 2022
- [c59]Alexis Duhamel, Sébastien Pillement:
QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded Systems. DASIP 2022: 96-107 - [c58]Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms, Kim Grüttner:
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms. SAMOS 2022: 250-263 - 2021
- [j18]Simei Yang, Sébastien Le Nours, Maria Mendez Real, Sébastien Pillement:
0-1 ILP-based run-time hierarchical energy optimization for heterogeneous cluster-based multi/many-core systems. J. Syst. Archit. 116: 102035 (2021) - [c57]Hai-Dang Vu, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Kim Grüttner:
A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC. ASP-DAC 2021: 17-22 - [c56]Hai-Dang Vu, Sébastien Le Nours, Sébastien Pillement:
Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems. DSD 2021: 150-157 - 2020
- [c55]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE 2020: 532-537 - [c54]Safouane Noubir, Maria Mendez Real, Sébastien Pillement:
Towards Malicious Exploitation of Energy Management Mechanisms. DATE 2020: 1043-1048 - [c53]Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI 2020: 386-391
2010 – 2019
- 2019
- [c52]Simei Yang, Sébastien Le Nours, Maria Mendez Real, Sébastien Pillement:
Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems. DASIP 2019: 29-34 - [c51]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Integer Dividers: Division by a Constant. ISVLSI 2019: 76-81 - [c50]Ralf Stemmer, Hai-Dang Vu, Kim Grüttner, Sébastien Le Nours, Wolfgang Nebel, Sébastien Pillement:
Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs. SAMOS 2019: 241-254 - [c49]Simei Yang, Sébastien Le Nours, Maria Mendez Real, Sébastien Pillement:
System-Level Modeling and Simulation of MPSoC Run-Time Management Using Execution Traces Analysis. SAMOS 2019: 281-293 - [c48]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC 2019: 257-262 - 2018
- [c47]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. EDCC 2018: 25-32 - [c46]Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel E. Holcomb, Russell Tessier:
FPGA Side Channel Attacks without Physical Access. FCCM 2018: 45-52 - [c45]Tien Thanh Nguyen, Mathieu Thevenin, Anthony Mouraud, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement:
High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. IPDPS Workshops 2018: 202-205 - 2017
- [j17]Wei He, Sébastien Pillement, Du Xu:
FTUC: A Flooding Tree Uneven Clustering Protocol for a Wireless Sensor Network. Sensors 17(12): 2706 (2017) - [j16]Shaoyang Men, Pascal Chargé, Sébastien Pillement:
Cooperative Spectrum Sensing with Small Sample Size in Cognitive Wireless Sensor Networks. Wirel. Pers. Commun. 96(2): 1871-1885 (2017) - [c44]Tien Thanh Nguyen, Anthony Mouraud, Mathieu Thevenin, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement:
Model-driven reliability evaluation for MPSoC design. DASIP 2017: 1-6 - 2016
- [c43]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware runtime verification of embedded software in SoPC. SIES 2016: 171-176 - 2015
- [j15]Shaoyang Men, Pascal Chargé, Sébastien Pillement:
A Robust and Energy Efficient Cooperative Spectrum Sensing Scheme in Cognitive Wireless Sensor Networks. Netw. Protoc. Algorithms 7(3): 140-156 (2015) - [c42]Shaoyang Men, Pascal Chargé, Sébastien Pillement:
A robust cooperative spectrum sensing method against faulty nodes in CWSNs. ICC Workshops 2015: 334-339 - [c41]B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak:
Fault-aware configurable logic block for reliable reconfigurable FPGAs. ISCAS 2015: 2732-2735 - 2014
- [j14]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38(2): 124-136 (2014) - [j13]Ludovic Devaux, Sébastien Pillement:
OCEAN, a flexible adaptive Network-On-Chip for dynamic applications. Microprocess. Microsystems 38(4): 337-357 (2014) - [c40]B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement:
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. ARC 2014: 254-261 - [c39]Romain Brillu, Sébastien Pillement, Fabrice Lemonnier, Philippe Millet, Eric Lenormand, Marc Bernot, Frédéric Falzon:
Towards a Design Space Exploration Tool for MPSoC Platforms Designs: A Case Study. PDP 2014: 466-473 - [c38]Romain Brillu, Sébastien Pillement, Aymen Abdellah, Fabrice Lemonnier, Philippe Millet:
FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture. RAPIDO 2014: 3:1-3:8 - [e1]Eduardo de la Torre, Sébastien Pillement:
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, October 8-10, 2014. IEEE 2014, ISBN 979-10-92279-06-1 [contents] - 2013
- [j12]Romain Brillu, Sébastien Pillement, Fabrice Lemonnier, Philippe Millet:
Cluster based MPSoC architecture: an on-chip message passing implementation. Des. Autom. Embed. Syst. 17(3-4): 587-607 (2013) - [j11]Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak:
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. IEEE Trans. Computers 62(6): 1179-1192 (2013) - [j10]Loïc Lagadec, Sébastien Pillement, Arnaud Tisserand:
Introduction. Tech. Sci. Informatiques 32(2): 149-151 (2013) - [c37]Quang-Hai Khuat, Quang-Hoa Le, Daniel Chillet, Sébastien Pillement:
Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. IDT 2013: 1-6 - 2012
- [c36]Istas Pratomo, Sébastien Pillement:
Gradient - An adaptive fault-tolerant routing algorithm for 2D mesh Network-on-Chips. DASIP 2012: 1-8 - [c35]Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet:
UPaRC - Ultra-fast power-aware reconfiguration controller. DATE 2012: 1373-1378 - [c34]Istas Pratomo, Sébastien Pillement:
Impact of design parameters on performance of adaptive Network-on-Chips. HPCS 2012: 724-725 - [c33]Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire:
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS 2012: 228-235 - 2011
- [j9]Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys:
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. J. Syst. Archit. 57(4): 340-353 (2011) - [c32]Hung-Manh Pham, Sébastien Pillement, Olivier Pasquier, Sébastien Le Nours:
A framework for the design of reconfigurable fault tolerant architectures. DASIP 2011: 324-331 - [c31]Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures. DDECS 2011: 441-446 - [c30]Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Parallel Evaluation of Hopfield Neural Networks. IJCCI (NCTA) 2011: 248-253 - [c29]Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Hardware OS Communication Service and Dynamic Memory Management for RSoCs. ReConFig 2011: 117-122 - [c28]Hung-Manh Pham, Ludovic Devaux, Sébastien Pillement:
Re2DA: Reliable and reconfigurable dynamic architecture. ReCoSoC 2011: 1-6 - [c27]Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. VLSI-SoC 2011: 196-199 - 2010
- [b1]Sébastien Pillement:
Conception d'architectures reconfigurables dynamiquement : Du silicium au système. (Dynamically reconfigurable architectures: From silicon to system management). University of Rennes 1, France, 2010 - [j8]Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14(8): 761-763 (2010) - [j7]Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2010: 390545:1-390545:15 (2010) - [j6]Sébastien Pillement, Olivier Sentieys, Jean-Marc Philippe:
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect. Microelectron. J. 41(8): 480-486 (2010) - [j5]Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 777-781 (2010) - [c26]Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Task placement for dynamic and partial reconfigurable architecture. DASIP 2010: 228-234 - [c25]Hung-Manh Pham, Sébastien Pillement, Didier Demigny:
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC. FPL 2010: 159-162 - [c24]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of a fault-tolerant coarse-grained. ISQED 2010: 845-852 - [c23]Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. ReConFig 2010: 376-381 - [c22]Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC 2010: 157-160
2000 – 2009
- 2009
- [j4]Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement:
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. Int. J. Reconfigurable Comput. 2009: 450607:1-450607:22 (2009) - [c21]Julien Lallet, Sébastien Pillement, Olivier Sentieys:
xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. DSD 2009: 680-687 - [c20]Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet:
High-Level Exploration for Dynamic Reconfiguration Management. ERSA 2009: 301-302 - [c19]Hung-Manh Pham, Sébastien Pillement, Didier Demigny:
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip. ReConFig 2009: 284-289 - 2008
- [j3]Sébastien Pillement, Olivier Sentieys, Raphaël David:
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency. EURASIP J. Embed. Syst. 2008 (2008) - [c18]Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement:
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig 2008: 61-66 - [c17]Julien Lallet, Sébastien Pillement, Olivier Sentieys:
Efficient dynamic reconfiguration for multi-context embedded FPGA. SBCCI 2008: 210-215 - 2007
- [j2]Sébastien Pillement, Raphaël David:
Architectures reconfigurable et faible consommation. Réalité ou prospective ? Tech. Sci. Informatiques 26(5): 595-621 (2007) - [c16]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282 - [c15]Imene Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Hardware task scheduling for heterogeneous soc architectures. EUSIPCO 2007: 1653-1657 - [c14]Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN 2007: 102-107 - 2006
- [c13]Jean-Marc Philippe, E. Kinvi-Boh, Sébastien Pillement, Olivier Sentieys:
An energy-efficient ternary interconnection link for asynchronous systems. ISCAS 2006 - [c12]Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys:
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. ISQED 2006: 334-339 - [c11]Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny:
Clear Stream towards Dynamically Reconfigurable Systems on Chip. ReCoSoC 2006: 98-104 - 2005
- [j1]Raphaël David, Dominique Lavenier, Sébastien Pillement:
Du microprocesseur au circuit FPGA. Une analyse sous l'angle de la reconfiguration. Tech. Sci. Informatiques 24(4): 395-422 (2005) - [c10]Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys:
A low-power and high-speed quaternary interconnection link using efficient converters. ISCAS (5) 2005: 4689-4692 - [c9]François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement:
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC 2005: 71-78 - 2002
- [c8]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL 2002: 1058-1067 - [c7]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. ICASSP 2002: 4194 - [c6]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS 2002 - [c5]Sébastien Pillement, Daniel Chillet, Olivier Sentieys:
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED 2002: 388-393 - 2001
- [c4]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC 2001: 51-62
1990 – 1999
- 1999
- [c3]S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres:
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. VLSI 1999: 407-414 - [c2]Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon:
Fast Prototyping: A Case Study - The JPEG Compression Algorithm. IEEE International Workshop on Rapid System Prototyping 1999: 87- - 1996
- [c1]Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon:
Concurrent Design of Hardware/Software Dedicated Systems. FPL 1996: 410-414
Coauthor Index
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