default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJosé L. Núñez-Yáñez
José Luis Núñez-Yáñez
Person information
- affiliation: University of Linköping, Sweden
- affiliation (former): University of Bristol, UK
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j47]Habib Taha Kose
, José L. Núñez-Yáñez, Robert J. Piechocki, James Pope:
A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems. Inf. 15(7): 377 (2024)- [j46]Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun:
Advanced Millimeter-Wave Radar System for Real-Time Multiple-Human Tracking and Fall Detection. Sensors 24(11): 3660 (2024) - [c74]Olle Hansson, Mahdieh Grailoo, Oscar Gustafsson, José L. Núñez-Yáñez:
Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. ARC 2024: 33-47 - [c73]Kaan Olgu, Tobias Kenter, José L. Núñez-Yáñez, Simon McIntosh-Smith:
Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures. IWOCL 2024: 6:1-6:11 - [c72]Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun:
MMIDNet: Secure Human Identification Using Millimeter-wave Radar and Deep Learning. MECO 2024: 1-7 - [c71]Mahdieh Grailoo, Tooraj Nikoubin, José L. Núñez-Yáñez:
Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform. NorCAS 2024: 1-6 - [c70]Olle Hansson, Oscar Gustafsson, José L. Núñez-Yáñez:
Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks. NorCAS 2024: 1-7 - [c69]Hadi Mousanejad Jeddi, Mahdieh Grailoo, José L. Núñez-Yáñez:
Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks. NorCAS 2024: 1-7 - [c68]José L. Núñez-Yáñez:
Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training. NorCAS 2024: 1-7 - 2023
- [j45]José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre:
Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems 98: 104801 (2023) - [c67]José L. Núñez-Yáñez:
Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows. ARC 2023: 131-145 - [c66]Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez:
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC 2023: 260-274 - [c65]Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun:
Multiple Human Tracking and Fall Detection Real-Time System Using Millimeter-Wave Radar and Data Fusion. MECO 2023: 1-6 - [c64]Simon Wegener, Kris K. Nikov, José L. Núñez-Yáñez, Kerstin Eder:
EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. WCET 2023: 9:1-9:14 - [i14]Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, José L. Núñez-Yáñez:
Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. CoRR abs/2301.12806 (2023) - [i13]José L. Núñez-Yáñez, Andrés Otero, Eduardo de la Torre:
Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite. CoRR abs/2304.08211 (2023) - [i12]Zichao Shen, Neil J. Howard, José L. Núñez-Yáñez:
Big-Little Adaptive Neural Networks on Low-Power Near-Subthreshold Processors. CoRR abs/2304.09695 (2023) - [i11]Simon Wegener, Kris K. Nikov, José L. Núñez-Yáñez, Kerstin Eder:
EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. CoRR abs/2305.14968 (2023) - 2022
- [j44]Kris Nikov, Marcos Martínez, Simon Wegener, José L. Núñez-Yáñez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder:
Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU. IEEE Embed. Syst. Lett. 14(3): 147-150 (2022) - [j43]Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo:
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. 124: 102398 (2022) - [j42]José L. Núñez-Yáñez:
Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite. IEEE Micro 42(6): 55-66 (2022) - [c63]Minxuan Kong, José Luis Núñez-Yáñez:
Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network. ARC 2022: 72-86 - [c62]Minxuan Kong, Kris Nikov, José Luis Núñez-Yáñez:
Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks. DSD 2022: 1-8 - [c61]Kaan Olgu, Kris Nikov, José L. Núñez-Yáñez:
Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications. DSD 2022: 16-23 - [c60]Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez:
A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher. DSD 2022: 101-108 - [c59]Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, José L. Núñez-Yáñez:
Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. ICECS 2022 2022: 1-4 - [d1]Kris Nikov, Marcos Martínez, Pedro Vallejo, Abel Balbis, José L. Núñez-Yáñez, Kerstin Eder:
GR712RC LEON3 Power Model Data. IEEE DataPort, 2022
- 2021
- [j41]José L. Núñez-Yáñez, Mohammad Hosseinabady:
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. Array 12: 100101 (2021) - [j40]José L. Núñez-Yáñez, Neil J. Howard:
Energy-efficient neural networks with near-threshold processors and hardware accelerators. J. Syst. Archit. 116: 102062 (2021) - [i10]Kris Nikov, Marcos Martínez, Simon Wegener, José L. Núñez-Yáñez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder:
Robust and accurate fine-grain power models for embedded systems with no on-chip PMU. CoRR abs/2106.00565 (2021) - 2020
- [j39]Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, José L. Núñez-Yáñez:
Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion. IEEE Access 8: 19033-19045 (2020) - [j38]Krastin Nikov, José L. Núñez-Yáñez:
Intra and inter-core power modelling for single-ISA heterogeneous processors. Int. J. Embed. Syst. 12(3): 324-340 (2020) - [j37]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1272-1285 (2020) - [j36]Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez:
Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J. Supercomput. 76(6): 4645-4665 (2020) - [c58]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. PARMA-DITAM@HiPEAC 2020: 1:1-1:6 - [c57]José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady:
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. PARMA-DITAM@HiPEAC 2020: 2:1-2:6 - [i9]Demetrios A. M. Coutinho, Daniele De Sensi, Arthur Francisco Lorenzon, Kyriakos Georgiou, José L. Núñez-Yáñez, Kerstin Eder, Samuel Xavier de Souza:
Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems. CoRR abs/2005.02947 (2020) - [i8]José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady:
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. CoRR abs/2006.12176 (2020) - [i7]Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez:
High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. CoRR abs/2008.08883 (2020) - [i6]Kris Nikov, José L. Núñez-Yáñez, Matthew Horsnell:
Evaluation of hybrid run-time power models for the ARM big.LITTLE architecture. CoRR abs/2008.10604 (2020)
2010 – 2019
- 2019
- [j35]Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez:
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. J. Syst. Archit. 98: 27-40 (2019) - [j34]José L. Núñez-Yáñez:
Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling. IEEE Trans. Computers 68(5): 676-687 (2019) - [j33]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4078-4095 (2019) - [j32]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4096-4097 (2019) - [c56]William Beasley, Brenda Gatusch, Daniel Connolly-Taylor, Chenyuan Teng, Asier Marzo, José L. Núñez-Yáñez:
Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays. AHS 2019: 41-48 - [c55]José L. Núñez-Yáñez:
Energy Proportional Heterogenous Computing with Reconfigurable MPSoC. HPCS 2019: 642 - [c54]Dave McEwan, José L. Núñez-Yáñez:
Relationship Estimation Metrics for Binary SoC Data. LOD 2019: 118-129 - [c53]Dave McEwan, Marcin Hlond, José L. Núñez-Yáñez:
Visualizations for Understanding SoC Behaviour. PRIME 2019: 277-280 - [c52]Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier de Souza:
Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications. VLSI-SoC 2019: 232-233 - [i5]Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez:
Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. CoRR abs/1901.06331 (2019) - [i4]William Beasley, Brenda Gatusch, Daniel Connolly-Taylor, Chenyuan Teng, Asier Marzo, José L. Núñez-Yáñez:
High-Performance Ultrasonic Levitation with FPGA-based Phased Arrays. CoRR abs/1901.07317 (2019) - [i3]Dave McEwan, José L. Núñez-Yáñez:
Relationship Detection Measures for Binary SoC Data. CoRR abs/1905.12465 (2019) - 2018
- [j31]Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas:
Reconfigurable Network Stream Processing on Virtualized FPGA Resources. Int. J. Reconfigurable Comput. 2018 (2018) - [j30]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Dynamic Energy Management of FPGA Accelerators in Embedded Systems. ACM Trans. Embed. Comput. Syst. 17(3): 63:1-63:26 (2018) - [c51]Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez:
Multi-precision convolutional neural networks on heterogeneous hardware. DATE 2018: 419-424 - [c50]Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez:
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. FPL 2018: 376-380 - [i2]José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR abs/1802.03316 (2018) - 2017
- [j29]José L. Núñez-Yáñez:
Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. Microprocess. Microsystems 51: 227-238 (2017) - [j28]Felipe Galindo Sanchez, José L. Núñez-Yáñez:
Energy proportional streaming spiking neural network in a reconfigurable system. Microprocess. Microsystems 53: 57-67 (2017) - [c49]Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, José L. Núñez-Yáñez:
Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding. EUSIPCO 2017: 1996-2000 - [c48]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. FPL 2017: 1-4 - [c47]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Pipelined Streaming Computation of Histogram in FPGA OpenCL. PARCO 2017: 632-641 - [c46]José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO 2017: 677-686 - [c45]Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas:
Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. ReConFig 2017: 1-6 - 2016
- [j27]Nuno Roma, José L. Núñez-Yáñez:
Editorial to special issue on energy efficient architectures for embedded systems. EURASIP J. Embed. Syst. 2016: 20 (2016) - [j26]José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi:
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. IEEE Trans. Computers 65(5): 1484-1493 (2016) - [c44]José L. Núñez-Yáñez:
Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application. ARC 2016: 41-53 - [c43]Peng Sun, Alin Achim, Ian Hasler, Paul R. Hill, José L. Núñez-Yáñez:
Energy efficient video fusion with heterogeneous CPU-FPGA devices. DATE 2016: 1399-1404 - [c42]Awais Hussain Sani, José Luis Núñez-Yáñez:
Energy proportional computing with OpenCL on a FPGA-based overlay architecture. NORCAS 2016: 1-6 - [c41]Mohd Amiruddin Zainol, José Luis Núñez-Yáñez:
CPCIe: A compression-enabled PCIe core for energy and performance optimization. NORCAS 2016: 1-6 - [i1]José L. Núñez-Yáñez, Tom Sun:
Energy Efficient Video Fusion with Heterogeneous CPU-FPGA Devices. CoRR abs/1602.02517 (2016) - 2015
- [j25]José L. Núñez-Yáñez, J. M. Moreno, Dimitrios S. Nikolopoulos:
Guest Editorial. IET Comput. Digit. Tech. 9(1): 1-2 (2015) - [j24]Juan Carlos Moctezuma, Joseph P. McGeehan, José Luis Núñez-Yáñez:
Biologically compatible neural networks with reconfigurable hardware. Microprocess. Microsystems 39(8): 693-703 (2015) - [j23]José Luis Núñez-Yáñez:
Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs. IEEE Trans. Computers 64(1): 45-53 (2015) - [c40]Krastin Nikov, José L. Núñez-Yáñez, Matthew Horsnell:
Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture. EUC 2015: 205-210 - [c39]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Energy optimization of FPGA-based stream-oriented computing with power gating. FPL 2015: 1-6 - [c38]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. FPL 2015: 1-6 - [c37]Rafael Asenjo, Angeles G. Navarro, Andrés Rodríguez, José L. Núñez-Yáñez:
Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB. PARCO 2015: 543-551 - 2014
- [j22]Arash Beldachi, Simon J. Hollis, José L. Núñez-Yáñez:
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip. IET Comput. Digit. Tech. 8(3): 148-162 (2014) - [j21]Arash Beldachi, José L. Núñez-Yáñez:
Run-time power and performance scaling in 28 nm FPGAs. IET Comput. Digit. Tech. 8(4): 178-186 (2014) - [j20]José L. Núñez-Yáñez:
Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. SIGARCH Comput. Archit. News 42(4): 87-92 (2014) - [j19]Jin Chen, José Luis Núñez-Yáñez, Alin Achim:
Bayesian Video Super-Resolution With Heavy-Tailed Prior Models. IEEE Trans. Circuits Syst. Video Technol. 24(6): 905-914 (2014) - [c36]José L. Núñez-Yáñez, Arash Beldachi:
Run-time power and performance scaling with CPU-FPGA hybrids. AHS 2014: 55-60 - [c35]Peng Sun, José L. Núñez-Yáñez:
Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compression. FPGAworld 2014: 2:1-2:7 - [c34]Arash Farhadi Beldachi, José L. Núñez-Yáñez:
Accurate power control and monitoring in ZYNQ boards. FPL 2014: 1-4 - [c33]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Run-time power gating in hybrid ARM-FPGA devices. FPL 2014: 1-6 - [c32]Yun Wu, José L. Núñez-Yáñez, Roger F. Woods, Dimitrios S. Nikolopoulos:
Power modelling and capping for heterogeneous ARM/FPGA SoCs. FPT 2014: 231-234 - [c31]Jin Chen, José L. Núñez-Yáñez, Alin Achim:
Joint video fusion and super resolution based on Markov random fields. ICIP 2014: 2150-2154 - [c30]Juan Carlos Moctezuma, José Luis Núñez-Yáñez, Joseph P. McGeehan:
Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation. IJCCI (NCTA) 2014: 85-93 - 2013
- [j18]José L. Núñez-Yáñez, Geza Lore:
Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip. Microprocess. Microsystems 37(3): 319-332 (2013) - [j17]Yiwei Zhang, Joseph McGeehan, Edward Regan, Stephen Kelly, José Luis Núñez-Yáñez:
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic. IEEE Trans. Computers 62(3): 599-608 (2013) - [c29]José L. Núñez-Yáñez:
Energy proportional computing in commercial FPGAs with adaptive voltage scaling. FPGAworld 2013: 6:1-6:5 - [c28]Jin Chen, José L. Núñez-Yáñez, Alin Achim:
Video super-resolution using low rank matrix completion. ICIP 2013: 1376-1380 - [c27]Juan Carlos Moctezuma, Joseph McGeehan, José Luis Núñez-Yáñez:
Numerically efficient and biophysically accurate neuroprocessing platform. ReConFig 2013: 1-6 - 2012
- [j16]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Comput. Digit. Tech. 6(1): 1-11 (2012) - [j15]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. IET Comput. Digit. Tech. 6(6): 384-395 (2012) - [j14]Xiaolin Chen, Nishan Canagarajah, José Luis Núñez-Yáñez, Raffaele Vitulli:
Lossless video compression based on backward adaptive pixel-based fast motion estimation. Signal Process. Image Commun. 27(9): 961-972 (2012) - [j13]Jin Chen, José L. Núñez-Yáñez, Alin Achim:
Video Super-Resolution Using Generalized Gaussian Markov Random Fields. IEEE Signal Process. Lett. 19(2): 63-66 (2012) - [j12]Atukem Nabina, José Luis Núñez-Yáñez:
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform. ACM Trans. Reconfigurable Technol. Syst. 5(4): 20:1-20:22 (2012) - [j11]José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis:
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 437-448 (2012) - [c26]Jin Chen, José L. Núñez-Yáñez, Alin Achim:
Approximate alpha-stable Markov Random Fields for video super-resolution. EUSIPCO 2012: 2738-2742 - [c25]José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady:
Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS 2012: 254-260 - 2011
- [j10]José L. Núñez-Yáñez, Trevor Spiteri, George Vafiadis:
Multi-standard reconfigurable motion estimation processor for hybrid video codecs. IET Comput. Digit. Tech. 5(2): 73-85 (2011) - 2010
- [c24]Mohammad Hosseinabady, José L. Núñez-Yáñez:
SystemC Architectural Transaction Level Modelling for Large NoCs. FDL 2010: 142-147 - [c23]Atukem Nabina, José L. Núñez-Yáñez:
Dynamic Reconfiguration Optimisation with Streaming Data Decompression. FPL 2010: 602-607 - [c22]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Effective modelling of large NoCs using SystemC. ISCAS 2010: 161-164 - [c21]Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola:
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. ISVLSI 2010: 167-172
2000 – 2009
- 2009
- [j9]Xiaolin Chen, Nishan Canagarajah, José L. Núñez-Yáñez:
Backward Adaptive Pixel-based Fast Predictive Motion Estimation. IEEE Signal Process. Lett. 16(5): 370-373 (2009) - [c20]José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi:
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC 2009: 308-313 - [c19]Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly:
A biophysically accurate floating point somatic neuroprocessor. FPL 2009: 26-31 - [c18]Trevor Spiteri, George Vafiadis, José Luis Núñez-Yáñez:
A toolset for the analysis and optimization of motion estimation algorithms and processors. FPL 2009: 423-428 - [c17]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Run-time resource management in fault-tolerant network on reconfigurable chips. FPL 2009: 574-577 - [c16]Wei Song, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta:
Adaptive stochastic routing in fault-tolerant on-chip networks. NOCS 2009: 32-37 - 2008
- [j8]José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola:
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tech. 2(3): 184-198 (2008) - [j7]Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos:
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integr. 41(1): 135-152 (2008) - [j6]Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall:
A Novel Delta Sigma Control System Processor and Its VLSI Implementation. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 217-228 (2008) - [c15]José Luis Núñez-Yáñez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli:
Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture. AHS 2008: 172-177 - [c14]Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez:
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. ARC 2008: 332-337 - [c13]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP 2008: 31-36 - [c12]Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez:
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. DSD 2008: 592-598 - [c11]José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras:
A configurable and programmable motion estimation processor for the H.264 video codec. FPL 2008: 149-154 - [c10]Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez:
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. FPL 2008: 547-550 - 2007
- [c9]José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler:
Dynamic Voltage Scaling in a FPGA-based System-on-Chip. FPL 2007: 459-462 - [c8]R. Stapenhurst, Koushik Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan:
On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005 - [c7]Xiaolin Chen, Nishan Canagarajah, José Luis Núñez-Yáñez, Raffaele Vitulli:
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding. SoCC 2007: 251-254 - 2006
- [j5]José L. Núñez-Yáñez, Vassilios A. Chouliaras, Daniele Alfonso, Fabrizio S. Rovati:
Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec. IEEE Trans. Consumer Electron. 52(2): 590-597 (2006) - [c6]Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova:
A Novel Processor Architecture for Real-Time Control. Asia-Pacific Computer Systems Architecture Conference 2006: 270-280 - 2005
- [j4]José L. Núñez-Yáñez, Vassilios A. Chouliaras:
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. IEEE Trans. Computers 54(11): 1345-1359 (2005) - [j3]José L. Núñez-Yáñez, Vassilios A. Chouliaras:
High-performance arithmetic coding VLSI macro for the H264 video compression standard. IEEE Trans. Consumer Electron. 51(1): 144-151 (2005) - [j2]Vassilios A. Chouliaras, José L. Núñez-Yáñez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso:
A multi-standard video accelerator based on a vector architecture. IEEE Trans. Consumer Electron. 51(1): 160-167 (2005) - [c5]Tom R. Jacobs, José L. Núñez-Yáñez:
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. ASAP 2005: 405-410 - [c4]José L. Núñez-Yáñez, Vassilios A. Chouliaras:
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP 2005: 411-416 - [c3]Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez:
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. ISVLSI 2005: 272-273 - [c2]Konstantia Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez:
Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. SIP 2005: 39-44 - 2003
- [j1]Vassilios A. Chouliaras, José L. Núñez-Yáñez:
Scalar coprocessors for accelerating the G723.1 and G729A speech coders. IEEE Trans. Consumer Electron. 49(3): 703-710 (2003) - [c1]E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez:
A code compression scheme for improving SoC performance. SoC 2003: 35-40 - 2001
- [b1]José Luis Núñez-Yáñez:
Gbit/second lossless data compression hardware. Loughborough University, UK, 2001
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-13 02:00 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
