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ORCIDAtsushi Muramatsu
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2010 – 2019
- 2017
[j4]Hiroyuki Nakamoto, Hong Gao
, Atsushi Muramatsu:
A Thin, Compact and Maintenance-Free Beacon Transmitter Operating from a 44-lux Photovoltaic Film Harvester. IEICE Trans. Electron. 100-C(6): 584-591 (2017)- 2012
- [c4]Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai:
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591 - 2011
- [j3]Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 294-298 (2011) - [c3]Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai:
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC 2011: 191-194 - 2010
- [c2]Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai:
Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631
2000 – 2009
- 2005
- [j2]Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera:
Effects of On-Chip Inductance on Power Distribution Grid. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3564-3572 (2005) - [c1]Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera:
Effects of on-chip inductance on power distribution grid. ISPD 2005: 63-69
1980 – 1989
- 1989
- [j1]Yoshifumi Sekine, Masatoshi Suyama, Atsushi Muramatsu:
Spatial feature detection using a pulse-type hardware neuron model. Syst. Comput. Jpn. 20(11): 1-10 (1989)
Coauthor Index
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