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ORCIDAlessandro Cevrero
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2020 – today
- 2020
[j11]Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg
, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf:
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55(1): 38-48 (2020)
2010 – 2019
- 2019
- [c35]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC 2019: 239-240 - [c34]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl:
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC 2019: 112-114 - [c33]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC 2019: 476-478 - 2018
- [j10]Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl:
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits 53(3): 861-872 (2018) - [j9]Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli:
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53(4): 1214-1226 (2018) - [j8]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(4): 1227-1237 (2018) - [j7]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang:
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(11): 3268-3279 (2018) - [j6]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(12): 3508-3516 (2018) - [c32]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl, Yusuf Leblebici:
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS 2018: 1-5 - [c31]Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Alessandro Cevrero, Marcel A. Kossel, Lukas Kull, Danny Luu, Ilter Özkaya, Thomas Toifl:
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. ISSCC 2018: 104-106 - [c30]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC 2018: 266-268 - [c29]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET. ISSCC 2018: 358-360 - [c28]Alessandro Cevrero, Ilter Özkaya, Thomas Morf, Thomas Toifl, M. Seifried, Frank Ellinger, Mohammad Mahdi Khafaji, Jan Plíva, Ronny Henker, Nikolay N. Ledentsov, J.-R. Kropp, V. A. Shchukin, M. Zoldak, L. Halmo, I. Eddie, Jaroslaw P. Turkiewicz:
4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS. OFC 2018: 1-3 - [c27]Thomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya:
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits 2018: 53-54 - [c26]Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl:
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits 2018: 267-268 - [c25]Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese, Matthias Braendli, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. VLSI Circuits 2018: 275-276 - 2017
- [j5]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52(12): 3458-3473 (2017) - [c24]Marcel A. Kossel, Christian Menolfi, Pier Andrea Francese, Lukas Kull, Thomas Morf, Thomas Toifl, Matthias Braendli, Alessandro Cevrero, Danny Luu, Ilter Özkaya, Hazar Yueksel:
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. ESSCIRC 2017: 115-118 - [c23]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang:
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ESSCIRC 2017: 183-186 - [c22]Ronny Henker, Thomas Toifl, Alessandro Cevrero, Ilter Oezkaya, Michael Georgiades, Mahdi M. Khafaji, Jan Plíva, Frank Ellinger:
Adaptive high-speed and ultra-low power optical interconnect for data center communications. ICTON 2017: 1-4 - [c21]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC 2017: 474-475 - [c20]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC 2017: 482-483 - 2016
- [j4]Giulia Beanato, Kiarash Gharibdoust, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici:
Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. Microelectron. J. 48: 50-59 (2016) - [j3]Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici:
Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors. Microelectron. J. 51: 38-45 (2016) - [c19]Thomas Toifl, Matthias Braendli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Ilter Özkaya, Hazar Yueksel:
Design considerations for 50G+ backplane links. ESSCIRC 2016: 477-482 - [c18]Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl:
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ISSCC 2016: 408-409 - 2015
- [c17]Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu:
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ISSCC 2015: 1-3 - [c16]Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, U. Bapst, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl:
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC 2015: 228- - 2014
- [c15]Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici:
3D serial TSV link for low-power chip-to-chip communication. ICICDT 2014: 1-4 - 2013
- [c14]Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508 - [c13]Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici:
3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. DATE 2013: 1241-1246 - [c12]Alexios Balatsoukas-Stimming, Nicholas Preyss, Alessandro Cevrero, Andreas Burg, Christoph Roth:
A parallelized layered QC-LDPC decoder for IEEE 802.11ad. NEWCAS 2013: 1-4 - 2012
- [j2]Giulia Beanato, Paolo Giovannini, Alessandro Cevrero, Panagiotis Athanasopoulos, Michael Zervas, Yuksel Temiz, Yusuf Leblebici:
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 295-306 (2012) - 2011
- [c11]Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici:
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC 2011: 1014-1019 - [c10]Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg:
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. ISCAS 2011: 1772-1775 - 2010
- [c9]Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici:
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. VLSI-SoC 2010: 149-154
2000 – 2009
- 2009
- [j1]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [c8]Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 - [c7]Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270 - [c6]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - [c5]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 - [c4]Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 - [c3]Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120 - 2008
- [c2]Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c1]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190
Coauthor Index
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