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ORCIDLi Shen 0007
Person information
- affiliation: National University of Defense Technology, School of Computer, Changsha, Hunan, China
Other persons with the same name
- Li Shen — disambiguation page
- Li Shen 0001
![[0000-0002-5443-0503]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-5443-0503")
— University of Pennsylvania, Philadelphia, USA (and 3 more) - Li Shen 0002 — Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China
- Li Shen 0003 — Institute for Infocomm Research, Singapore
- Li Shen 0004 — Southwest Jiaotong University, Faculty of Geosciences and Environmental Engineering, Chengdu, China (and 1 more)
- Li Shen 0005 — Alibaba Group, Beijing, China (and 3 more)
- Li Shen 0006 — Osaka University, Graduate School of Information Science and Technology, Japan
- Li Shen 0008 — Sun Yat-sen University Shenzhen Campus, School of Cyber Science and Technology, Shenzhen, China (and 3 more)
- Li Shen 0009 — Beihang University, School of Automation Science and Electrical Engineering, Beijing, China
- Li Shen 0010 — Huazhong University of Science and Technology, School of Optical and Electronic Information, Wuhan, China
- Li Shen 0011 — Beijing Institute of Remote Sensing, China
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2020 – today
- 2024
[j27]Chenyang Jiao, Zhikai Qin, Li Shen:
ScalaQC: a scalability optimization framework for full-state quantum simulation on CPU+GPU heterogeneous clusters. CCF Trans. High Perform. Comput. 6(4): 397-407 (2024)- [j26]Dunbo Zhang, Qingjie Lang, Ruoxi Wang, Li Shen:
Extension VM: Interleaved Data Layout in Vector Memory. ACM Trans. Archit. Code Optim. 21(1): 18:1-18:23 (2024) - [j25]Hongbing Tan, Libo Huang, Zhong Zheng, Hui Guo, Qianming Yang, Li Shen, Gang Chen, Liquan Xiao, Nong Xiao:
A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 681-693 (2024) - [j24]Liang Li, Siwei Wang, Xinwang Liu, En Zhu, Li Shen, Kenli Li, Keqin Li:
Local Sample-Weighted Multiple Kernel Clustering With Consensus Discriminative Graph. IEEE Trans. Neural Networks Learn. Syst. 35(2): 1721-1734 (2024) - [j23]Run Yan, Yin Su, Hui Guo, Yashuai Lü, Jin Wang, Nong Xiao, Li Shen, Yongwen Wang, Libo Huang:
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 396-400 (2024) - [c66]Chen Chen, Li Shen, Yingwen Chen:
A Distributed Framework for Subgraph Isomorphism Leveraging CPU and GPU Heterogeneous Computing. ICPP 2024: 433-442 - 2023
- [j22]Run Yan, Libo Huang, Hui Guo, Yashuai Lü, Ling Yang, Nong Xiao, Li Shen, Mengqiao Lan, Yongwen Wang:
MMsRT: A Hardware Architecture for Ray Tracing in the Mobile Domain. J. Circuits Syst. Comput. 32(11): 2350192:1-2350192:14 (2023) - [j21]Yuanwei Li, En Zhu, Hang Chen, Jiyong Tan, Li Shen:
Dense Crosstalk Feature Aggregation for Classification and Localization in Object Detection. IEEE Trans. Circuits Syst. Video Technol. 33(6): 2683-2695 (2023) - [j20]Tiejian Zhang, Xinwang Liu, Lei Gong, Siwei Wang, Xin Niu, Li Shen:
Late Fusion Multiple Kernel Clustering With Local Kernel Alignment Maximization. IEEE Trans. Multim. 25: 993-1007 (2023) - [c65]Shangshang Yao, Li Shen:
ImprLM: An Improved Logarithmic Multiplier Design Approach via Iterative Linear-Compensation and Modified Dynamic Segment. ICCD 2023: 66-69 - [c64]Chenyang Jiao, Weihua Zhang, Li Shen:
Communication Optimizations for State-vector Quantum Simulator on CPU+GPU Clusters. ICPP 2023: 203-212 - [i2]Xinhang Wan, Jiyuan Liu, Xinwang Liu, Siwei Wang, Yi Wen, Tianjiao Wan, Li Shen, En Zhu:
One-step Multi-view Clustering with Diverse Representation. CoRR abs/2306.05437 (2023) - 2022
- [j19]Ling Yang, Libo Huang, Run Yan, Nong Xiao, Sheng Ma, Li Shen, Weixia Xu:
Stride Equality Prediction for Value Speculation. IEEE Comput. Archit. Lett. 21(2): 57-60 (2022) - [j18]Dunbo Zhang, Chaoyang Jia, Li Shen:
Compressed page walk cache. Frontiers Comput. Sci. 16(3): 163104 (2022) - [c63]Run Yan, Libo Huang, Hui Guo, Yashuai Lü, Ling Yang, Nong Xiao, Li Shen, Yongwen Wang:
RTA: an Efficient SIMD Architecture for Ray Tracing. HPCC/DSS/SmartCity/DependSys 2022: 43-50 - [c62]Tao Li, Li Shen, Shangshang Yao:
A High-performance SpMV Accelerator on HBM-equipped FPGAs. HPCC/DSS/SmartCity/DependSys 2022: 1081-1087 - [c61]Yi Wei, Lin Deng, Sizheng Sun, Sisi Li, Li Shen:
DGEMM Optimization Oriented to ARM SVE Instruction Set Architecture. ICPADS 2022: 514-521 - [c60]Zhikai Qin, Tao Li, Li Shen:
DLC: An Optimization Framework for Full-State Quantum Simulation. NPC 2022: 207-218 - [i1]Liang Li, Siwei Wang, Xinwang Liu, En Zhu, Li Shen, Kenli Li, Keqin Li:
Local Sample-weighted Multiple Kernel Clustering with Consensus Discriminative Graph. CoRR abs/2207.02846 (2022) - 2021
- [j17]Ya-Shuai Lü, Hui Guo, Libo Huang, Qi Yu, Li Shen, Nong Xiao, Zhiying Wang:
GraphPEG: Accelerating Graph Processing on GPUs. ACM Trans. Archit. Code Optim. 18(3): 30:1-30:24 (2021) - [c59]Yang Lin, Dunbo Zhang, Chaoyang Jia, Qiong Wang, Li Shen:
Multi-level PWB and PWC for Reducing TLB Miss Overheads on GPUs. ICA3PP (2) 2021: 33-52 - [c58]Jingyu Liu, Dunbo Zhang, Qiong Wang, Li Shen:
A Multi-precision Quantized Super-Resolution Model Framework. ICA3PP (1) 2021: 336-353 - [c57]Shangshang Yao, Liang Zhang, Qiong Wang, Li Shen:
An Efficient Hybrid Parallel Compression Approximate Multiplier. ICCD 2021: 109-116 - [c56]Yang Lin, Dunbo Zhang, Chaoyang Jia, Qiong Wang, Li Shen:
Reducing TLB Miss Penalty on GPUs via Unified Multi-level PWB and PWC. PAAP 2021: 1-8 - 2020
- [j16]Shiqing Zhang, Zheng Qin, YaoHua Yang, Li Shen, Zhiying Wang:
Transparent partial page migration between CPU and GPU. Frontiers Comput. Sci. 14(3): 143101 (2020) - [c55]Juan Chen, John Impagliazzo, Li Shen:
High-Performance Computing and Engineering Educational Development and Practice. FIE 2020: 1-8 - [c54]Dunbo Zhang, Chaoyang Jia, Qiong Wang, Li Shen:
A Unified Page Walk Buffer and Page Walk Cache. ISPA/BDCloud/SocialCom/SustainCom 2020: 93-101 - [c53]Ninghui Yuan, Jingyu Liu, Qiong Wang, Li Shen:
Customizing Super-Resolution Framework According to Image Features. ISPA/BDCloud/SocialCom/SustainCom 2020: 1189-1196 - [c52]Ninghui Yuan, Dunbo Zhang, Qiong Wang, Li Shen:
A Multi-model Super-Resolution Training and Reconstruction Framework. NPC 2020: 105-116
2010 – 2019
- 2019
- [j15]Qiong Wang, Ning Li, Li Shen, Zhiying Wang:
A statistic approach for power analysis of integrated GPU. Soft Comput. 23(3): 827-836 (2019) - [c51]Juan Chen, Yingjun Cao, Linlin Du, Youwen Ouyang, Li Shen:
Improve Student Performance Using Moderated Two-Stage Projects. CompEd 2019: 201-207 - [c50]YaoHua Yang, Shiqing Zhang, Li Shen:
A Lightweight Method for Handling Control Divergence in GPGPUs. HPC Asia 2019: 120-127 - [c49]Ninghui Yuan, Zhihao Zhu, Xinzhou Wu, Li Shen:
MMSR: A Multi-model Super Resolution Framework. NPC 2019: 197-208 - 2018
- [j14]Qi Zhu, Bo Wu, Xipeng Shen, Kai Shen, Li Shen, Zhiying Wang:
Resolving the GPU responsiveness dilemma through program transformations. Frontiers Comput. Sci. 12(3): 545-559 (2018) - [j13]Sijiang Fan, Jiawei Fei, Li Shen:
Accelerating Deep Learning with a Parallel Mechanism Using CPU + MIC. Int. J. Parallel Program. 46(4): 660-673 (2018) - [c48]Juan Chen, Li Shen:
Design of paper CPU project to improve student understanding of CPU working principle. TURC 2018: 96-102 - [c47]Juan Chen, Li Shen, Jianping Yin, Chunyuan Zhang:
Parallel programming course development based on parallel computational thinking. TURC 2018: 103-109 - [c46]YaoHua Yang, Shiqing Zhang, Li Shen:
Control Divergence Optimization through Partial Warp Regrouping in GPGPUs. CSAI/ICIMT 2018: 369-374 - [c45]Shiqing Zhang, YaoHua Yang, Li Shen, Zhiying Wang:
Efficient Data Communication between CPU and GPU through Transparent Partial-Page Migration. HPCC/SmartCity/DSS 2018: 618-625 - [c44]Sheng Ma, Hongyi Lu, Libo Huang, Li Shen, Yang Guo, Zhiying Wang, Wenliang Xue:
Adaptive VC Partitioning for NoCs in GPGPUs. ISCAS 2018: 1-5 - [c43]Li Shen, Shiqing Zhang, YaoHua Yang, Zhiying Wang:
GPU Memory Management Solution Supporting Incomplete Pages. NPC 2018: 174-178 - [c42]Juan Chen, Li Shen, Jianping Yin, Chunyuan Zhang:
Design of Practical Experiences to Improve Student Understanding of Efficiency and Scalability Issues in High Performance Computing: (Abstract Only). SIGCSE 2018: 1090 - 2017
- [j12]Qi Zhu, Bo Wu, Xipeng Shen, Kai Shen, Li Shen, Zhiying Wang:
Understanding co-run performance on CPU-GPU integrated processors: observations, insights, directions. Frontiers Comput. Sci. 11(1): 130-146 (2017) - [j11]Jialong Wang, Yanhong Liu, Li Shen:
线程级猜测并行系统代码自动生成工具的设计与实现 (Design and Implementation of Automatic Code Generator for TLS System). 计算机科学 44(11): 114-119 (2017) - [j10]Libo Huang, Ya-Shuai Lü, Li Shen, Zhiying Wang:
Improving the Efficiency of GPGPU Work-Queue Through Data Awareness. ACM Trans. Archit. Code Optim. 14(4): 45:1-45:22 (2017) - [c41]Qiong Wang, Jialong Wang, Li Shen, Zhiying Wang:
A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation. CIT 2017: 184-191 - [c40]Ya-Shuai Lü, Libo Huang, Li Shen:
POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs. PACT 2017: 142-143 - [c39]Qiong Wang, Ning Li, Li Shen, Zhiying Wang:
A Novel Statistical Power Model for Integrated GPU with Optimization. ICPCSEE (2) 2017: 311-324 - [c38]Qi Zhu, Bo Wu, Xipeng Shen, Li Shen, Zhiying Wang:
Co-Run Scheduling with Power Cap on Integrated CPU-GPU Systems. IPDPS 2017: 967-977 - [c37]Sijiang Fan, Jiawei Fei, Ximing He, Li Shen, Zhiying Wang:
OTR: A Fine-Grained Dynamic Power Scaling Pipeline Based on Trace. ISPA/IUCC 2017: 275-281 - [c36]Sijiang Fan, Shiqing Zhang, Ximing He, Jiawei Fei, Li Shen, Zhiying Wang:
Parallel Computing in DNNs Using CPU and MIC. ISPA/IUCC 2017: 646-652 - [c35]Ya-Shuai Lü, Libo Huang, Li Shen, Zhiying Wang:
Unleashing the power of GPU for physically-based rendering via dynamic ray shuffling. MICRO 2017: 560-573 - [c34]Xinming Zhang, YaoHua Yang, Li Shen:
Spark-SIFT: A Spark-Based Large-Scale Image Feature Extract System. SKG 2017: 69-76 - 2016
- [j9]Li Shen, Fan Xu, Zhiying Wang:
Optimization Strategies Oriented to Loop Characteristics in Software Thread Level Speculation Systems. J. Comput. Sci. Technol. 31(1): 60-76 (2016) - [j8]Qi Yu, Boqian Wang, Li Shen, Zhiying Wang, Wei Chen:
GPU平台上面向性能和功耗的分支优化 (Branch Divergence Optimization for Performance and Power Consumption on GPU Platform). 计算机科学 43(5): 22-26 (2016) - [j7]Boqian Wang, Qi Yu, Xin Liu, Li Shen, Zhiying Wang, Wei Chen:
面向Cassandra数据库的高效动态数据管理机制 (Efficient and Dynamic Data Management System for Cassandra Database). 计算机科学 43(7): 197-202 (2016) - [c33]Jingwei Chen, Qiong Wang, Bo Su, Li Shen, Zhiying Wang:
A Hybrid Power-Performance Adjustment Strategy for Clustered Multi-threading Architecture. HPCC/SmartCity/DSS 2016: 292-300 - [c32]Wenjie Liu, Li Shen, Zhiying Wang:
A lightweight instruction-set simulator for teaching of dynamic instruction scheduling. ICCSE 2016: 871-876 - [c31]Ning Li, Li Shen, Qi Zhu, Yemao Xu, Jialong Wang, Zhiying Wang:
An implementation of analytical power model on integrated GPU. ISIC 2016: 1-4 - [c30]Jingwei Chen, Li Shen, Zhiying Wang, Ning Li, Yemao Xu:
Dynamic Power-Performance Adjustment on Clustered Multi-Threading Processors. NAS 2016: 1-2 - [c29]Yemao Xu, Jialong Wang, Yanhong Liu, Li Shen:
Fast Task Submission in Software Thread Level Speculation Systems. Trustcom/BigDataSE/ISPA 2016: 2160-2166 - 2014
- [j6]Xuhao Chen, Li Shen, Zhiying Wang, Zhong Zheng, Wei Chen:
Binary compatibility for embedded systems using greedy subgraph mapping. Sci. China Inf. Sci. 57(7): 1-16 (2014) - [j5]Libo Huang, Li Shen, Yashuai Lv, Zhiying Wang, Kui Dai:
Mac or Non-MAC: not a Problem. J. Circuits Syst. Comput. 23(5) (2014) - [j4]Sheng Ma, Zhiying Wang, Natalie D. Enright Jerger, Li Shen, Nong Xiao:
Novel Flow Control for Fully Adaptive Routing in Cache-Coherent NoCs. IEEE Trans. Parallel Distributed Syst. 25(9): 2397-2407 (2014) - [c28]Fan Xu, Li Shen, Zhiying Wang, Hui Guo, Bo Su, Wei Chen:
Customized Core Layout: A Case Study on Dual-Core Dynamic Binary Translation System. CIT 2014: 246-251 - [c27]Xin Liu, Li Shen, Cheng Qian, Zhiying Wang:
Dynamic Power Estimation with Hardware Performance Counters Support on Multi-core Platform. ACA 2014: 177-189 - [c26]Fan Xu, Li Shen, Zhiying Wang, Hui Guo, Bo Su, Wei Chen:
Improving Speculation Accuracy with Inter-thread Fetching Value Prediction. ICA3PP (2) 2014: 245-258 - [c25]Qi Zhu, Bo Wu, Xipeng Shen, Li Shen, Zhiying Wang:
Understanding Co-run Degradations on Integrated Heterogeneous Processors. LCPC 2014: 82-97 - [c24]Bo Su, Junli Gu, Li Shen, Wei Huang, Joseph L. Greathouse, Zhiying Wang:
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration. MICRO 2014: 445-457 - [c23]Bo Su, Joseph L. Greathouse, Junli Gu, Michael Boyer, Li Shen, Zhiying Wang:
Implementing a Leading Loads Performance Predictor on Commodity Processors. USENIX ATC 2014: 205-210 - 2013
- [j3]Zhong Zheng, Zhiying Wang, Li Shen:
Region-Based Way-Partitioning on L1 Data Cache for Low Power. IEICE Trans. Inf. Syst. 96-D(11): 2466-2469 (2013) - [c22]Bo Su, Li Shen, Lei Wang, Zhiying Wang, Yourui Wang, Libo Huang, Wei Shi:
DCP: Improving the Throughput of Asynchronous Pipeline by Dual Control Path. HPCC/EUC 2013: 230-237 - [c21]Fan Xu, Li Shen, Zhiying Wang, Hui Guo, Bo Su, Wei Chen:
HEUSPEC: A Software Speculation Parallel Model. ICPP 2013: 621-630 - 2012
- [j2]Libo Huang, Sheng Ma, Li Shen, Zhiying Wang, Nong Xiao:
Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support. IEEE Trans. Computers 61(5): 745-751 (2012) - [c20]Jiahui Wen, Li Shen, Zhiying Wang:
Dynamic Optimization on Multi-core Platform. TrustCom 2012: 1901-1906 - 2011
- [c19]Libo Huang, Zhiying Wang, Li Shen, Hongyi Lu, Nong Xiao, Cong Liu:
A specialized low-cost vectorized loop buffer for embedded processors. DATE 2011: 1200-1203 - [c18]Wei Shi, Weixia Xu, Hongguang Ren, Qiang Dou, Zhiying Wang, Li Shen, Cong Liu:
A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer. ICCD 2011: 267-272 - [c17]Xuhao Chen, Wei Chen, Jiawen Li, Zhong Zheng, Li Shen, Zhiying Wang:
Characterizing Fine-Grain Parallelism on Modern Multicore Platform. ICPADS 2011: 941-946 - [c16]Xuhao Chen, Zhong Zheng, Li Shen, Wei Chen, Zhiying Wang:
GSM: An Efficient Code Generation Algorithm for Dynamic Binary Translator. PAAP 2011: 231-235 - 2010
- [c15]Fan Xu, Li Shen, Zhiying Wang:
A Dynamic Binary Translation Framework Based on Page Fault Mechanism in Linux Kernel. CIT 2010: 2284-2289 - [c14]Libo Huang, Li Shen, Zhiying Wang, Wei Shi, Nong Xiao, Sheng Ma:
SIF: Overcoming the limitations of SIMD devices via implicit permutation. HPCA 2010: 1-12 - [c13]Libo Huang, Li Shen, Zhiying Wang:
Permutation optimization for SIMD devices. ISCAS 2010: 3849-3852
2000 – 2009
- 2009
- [j1]Ya-Shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao:
Optimal subgraph covering for customisable VLIW processors. IET Comput. Digit. Tech. 3(1): 14-23 (2009) - [c12]Wei Chen, Zhiying Wang, Hongyi Lu, Li Shen, Nong Xiao, Zhong Zheng:
A Hardware Approach for Reducing Interpretation Overhead. CIT (1) 2009: 98-103 - [c11]Ya-Shuai Lü, Li Shen, Zhiying Wang, Nong Xiao:
Dynamically utilizing computation accelerators for extensible processors in a software approach. CODES+ISSS 2009: 51-60 - [c10]Wei Chen, Li Shen, Hongyi Lu, Zhiying Wang, Nong Xiao:
A Light-weight Code Cache Design for Dynamic Binary Translation. ICPADS 2009: 120-125 - [c9]Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao:
Using Pcache to Speedup Interpretation in Dynamic Binary Translation. ISPA 2009: 525-530 - 2008
- [c8]Ya-Shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao:
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. DAC 2008: 197-200 - [c7]Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao:
DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture. EUC (2) 2008: 399-404 - [c6]Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao, Dan Chen:
A Novel Hardware Assisted Full Virtualization Technique. ICYCS 2008: 1292-1297 - [c5]Xinbiao Gan, Kui Dai, Libo Huang, Li Shen, Zhiying Wang:
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture. MUE 2008: 83-86 - 2007
- [c4]Libo Huang, Li Shen, Kui Dai, Zhiying Wang:
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. IEEE Symposium on Computer Arithmetic 2007: 69-76 - [c3]Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen:
Hardware Support for Arithmetic Units of Processor with Multimedia Extension. MUE 2007: 633-637 - 2004
- [c2]Ming-che Lai, Kui Dai, Li Shen, Zhiying Wang:
A New Technique for Program Code Compression in Embedded Microprocessor. ICESS 2004: 158-164 - 2003
- [c1]Li Shen, Zhiying Wang, Jianzhuang Lu:
Predicate Analysis Based on Path Information. APPT 2003: 147-151
Coauthor Index
[j17] [j16] [j15] [j14] [c45] [c44] [c43] [j12] [j10] [c41] [c39] [c38] [c37] [c36] [c35] [j9] [j8] [j7] [c33] [c32] [c31] [c30] [j6] [j5] [j4] [c28] [c27] [c26] [c25] [c24] [c23] [j3] [c22] [c21] [j2] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j1] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c2] [c1]
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