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2010 – 2019
- 2016
[c4]Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai:
15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique. ISSCC 2016: 280-281- 2013
- [j4]Tieng Yi Choke, Hongke Zhang, Sam Chun-Geik Tan, W. Yang, Ying Chow Tan, Satyanarayana Reddy Karri, Yuan Sun, Dan Ping Li, Zwei-Mei Lee, Tianbao Gao, Weimin Shu, Osama Shana'a
:
A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS. IEEE J. Solid State Circuits 48(5): 1174-1187 (2013) - 2011
- [c3]Chen-Yen Ho, Zwei-Mei Lee, Mu-Chen Huang, Sheng-Jui Huang:
A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application. A-SSCC 2011: 261-264
2000 – 2009
- 2007
- [j3]Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration. IEEE J. Solid State Circuits 42(10): 2149-2160 (2007) - 2006
- [c2]Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration. CICC 2006: 209-212 - 2005
- [j2]Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits 40(5): 1047-1056 (2005) - [j1]Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration". IEEE J. Solid State Circuits 40(11): 2339 (2005) - 2003
- [c1]Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
A digital background calibration technique for pipelined analog-to-digital converters. ISCAS (1) 2003: 881-884
Coauthor Index
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