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2020 – today
- 2024
[c44]Kenji Hisazumi, Takeshi Ohkawa, Masafumi Miwa, Mikiko Sato, Takashi Nagai
, Nobuhiro Ohe, Kittikhun Thongpull, Nattha Jindapetch, Harumi Watanabe:
APRIS Robot Challenge: Collaborative Online Interdisciplinary and International Learning for IoT/Robotics Systems. EDUCON 2024: 1-8- [c43]Xinyuan Zhu, Yuji Sato, Mikiko Sato:
The Optimal Zone Breadth for Parallel and Distributed MOEA/D with Virtual Overlap Zone and Exclusively Evaluated Mating. GECCO Companion 2024: 395-398 - 2023
- [c42]Hayato Mori, Eisuke Okazaki, Gai Nagahashi, Mikiko Sato, Takeshi Ohkawa, Midori Sugaya:
Offloading Image Recognition Processing for Care Robots to FPGA on Multi-access Edge Computing. ICFPT 2023: 270-271 - [c41]Yuji Sato, Mads A. Midtlyng, Mikiko Sato:
Diffusely Distributed Parallelization of MOEA/D with Edge Weight Vectors Sharing. GECCO Companion 2023: 411-414 - 2022
- [j5]Yuji Sato, Mikiko Sato:
Using Dominated Solutions at Edges to the Diversity and the Uniformity of Non-dominated Solution Distributions in NSGA-II. SN Comput. Sci. 3(6): 432 (2022) - 2021
- [c40]Mikiko Sato, Yuji Sato, Mads A. Midtlyng, Minami Miyakawa:
Inconstant Update of Reference Point Value for Parallel and Distributed MOEA/D. CEC 2021: 1495-1502 - [c39]Chinatsu Yamamoto, Ikuta Tanigawa, Kenji Hisazumi, Mikiko Sato, Takeshi Ohkawa, Nobuhiko Ogura, Harumi Watanabe:
Layer Modeling and Its Code Generation based on Context-oriented Programming. MODELSWARD 2021: 330-336 - 2020
- [c38]Yuji Sato, Mikiko Sato, Mads A. Midtlyng, Minami Miyakawa:
Parallel and Distributed MOEA/D with Exclusively Evaluated Mating and Migration. CEC 2020: 1-8
2010 – 2019
- 2019
- [c37]Yuji Sato, Mikiko Sato, Minami Miyakawa:
Distributed NSGA-II Sharing Extreme Non-dominated Solutions for Improving Accuracy and Achieving Speed-up. CEC 2019: 3086-3093 - [c36]Takeshi Ohkawa, Shotaro Tayama, Hayato Mori, Dohyung Lee, Hayato Amano, Itsuki Hirakawa, Mikiko Sato, Harumi Watanabe:
Design and Development of Networked Multiple FPGA Components for Autonomous Tiny Robot Car. FPT 2019: 473-475 - [c35]Takeshi Ohkawa, Ikuta Tanigawa, Mikiko Sato, Kenji Hisazumi, Nobuhiko Ogura, Harumi Watanabe:
Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming. MCSoC 2019: 116-122 - 2018
- [c34]Yuji Sato, Mikiko Sato, Minami Miyakawa:
Distributed NSGA-II sharing extreme non-dominated solutions. GECCO (Companion) 2018: 69-70 - [c33]Harumi Watanabe, Mikiko Sato, Masafumi Miwa, Makoto Imamura, Shintaro Hosoai, Nobuhiko Ogura, Hiroyuki Nakamura, Kenji Hisazumi:
Compulsory Game based Robot Contest for Embedded System Development Education. ICSCA 2018: 259-263 - [c32]Harumi Watanabe, Mikiko Sato, Masafumi Miwa, Makoto Imamura, Shintaro Hosoai, Nobuhiko Ogura, Hiroyuki Nakamura, Kenji Hisazumi:
Multidisciplinary skill assessment for embedded software development education via a robot contest. ICSE (Companion Volume) 2018: 151-152 - [c31]Minami Miyakawa, Hiroyuki Sato, Haruka Matsumoto, Mariko Tanaka, Mikiko Sato, Yuji Sato:
Effects of Duplication Operator in Evolutionary Simultaneous Design Optimization of Multiple Cars. SCIS&ISIS 2018: 478-484 - [c30]Harumi Watanabe, Mikiko Sato, Masafumi Miwa, Makoto Imamura, Shintaro Hosoai, Nobuhiko Ogura, Hiroyuki Nakamura, Kenji Hisazumi:
Assessment Map for Multidisciplinary Abilities for IoT System Development Education based on a Robot Contest. TALE 2018: 995-1000 - 2017
- [c29]Yuji Sato, Mikiko Sato, Minami Miyakawa:
Distributed NSGA-II with migration using compensation on many-core processors for improving performance and accuracy. GECCO (Companion) 2017: 161-162 - 2016
- [j4]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - 2015
- [j3]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - 2014
- [j2]Yuji Sato, Mikiko Sato:
Parallelization and sustainability of distributed genetic algorithms on many-core processors. Int. J. Intell. Comput. Cybern. 7(1): 2-23 (2014) - [c28]Motoki Wada, Mikiko Sato, Mitaro Namiki:
A fine grained power management supported by just-in-time compiler. COOL Chips 2014: 1-3 - [c27]Mikiko Sato, Shigeyoshi Tsutsui, Noriyuki Fujimoto, Yuji Sato, Mitaro Namiki:
First results of performance comparisons on many-core processors in solving QAP with ACO: kepler GPU versus xeon PHI. GECCO (Companion) 2014: 1477-1478 - [c26]Hiroshi Miyata, Mitaro Namiki, Mikiko Sato:
pmqFlow: Design of propagation time measuring QoS system with OpenFlow for process automation. IECON 2014: 3693-3699 - [c25]Yuichi Tsujita, Kazumi Yoshinaga, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
Multithreaded Two-Phase I/O: Improving Collective MPI-IO Performance on a Lustre File System. PDP 2014: 232-235 - [c24]Mikiko Sato, Go Fukazawa, Akio Shimada, Atsushi Hori, Yutaka Ishikawa, Mitaro Namiki:
Design of Multiple PVAS on InfiniBand Cluster System Consisting of Many-core and Multi-core. EuroMPI/ASIA 2014: 133 - 2013
- [c23]Yuji Sato, Mikiko Sato:
Parallelization and fault-tolerance of evolutionary computation on many-core processors. IEEE Congress on Evolutionary Computation 2013: 2602-2609 - [c22]Tetsuro Honmura, Yuki Kondo, Tetsuya Yamada, Masashi Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, Hirofumi Nishi, Mikiko Sato, Mitaro Namiki:
Hardware support for resource partitioning in real-time embedded systems. COOL Chips 2013: 1-3 - [c21]Yuji Sato, Mikiko Sato:
Fault-tolerance of distributed genetic algorithms on many-core processors. GECCO (Companion) 2013: 1749-1750 - [c20]Hiroshi Miyata, Mitaro Namiki, Mikiko Sato:
sQoS: The design and prototyping of secure QoS for process automation system. IECON 2013: 5680-5685 - [c19]Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI. PDP 2013: 249-253 - [c18]Yuichi Tsujita, Kazumi Yoshinaga, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
Improving Parallel I/O Performance Using Multithreaded Two-Phase I/O with Processor Affinity Management. PPAM (1) 2013: 714-723 - [p1]Yuji Sato, Naohiro Hasegawa, Mikiko Sato:
Acceleration of Genetic Algorithms for Sudoku Solution on Many-Core Processors. Massively Parallel Evolutionary Computation on GPGPUs 2013: 421-444 - 2012
- [j1]Yuji Sato, Hazuki Inoue, Mikiko Sato:
Parallelization of genetic operations that takes building-block linkage into account. Artif. Life Robotics 17(1): 17-23 (2012) - [c17]Mikiko Sato, Go Fukazawa, Kiyohiko Nagamine, Ryuichi Sakamoto, Mitaro Namiki, Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Yutaka Ishikawa:
A design of hybrid operating system for a parallel computer with multi-core and many-core processors. ROSS@ICS 2012: 9:1-9:8 - [c16]Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa:
Delegation-Based MPI Communications for a Hybrid Parallel Computer with Many-Core Architecture. EuroMPI 2012: 47-56 - [c15]Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki:
An OpenCL Runtime Library for Embedded Multi-Core Accelerator. RTCSA 2012: 419-422 - 2011
- [c14]Yuji Sato, Naohiro Hasegawa, Mikiko Sato:
GPU acceleration for Sudoku solution with genetic operations. IEEE Congress on Evolutionary Computation 2011: 296-303 - [c13]Yuji Sato, Naohiro Hasegawa, Mikiko Sato:
Acceleration of genetic algorithms for sudoku solution on many-core processors. GECCO (Companion) 2011: 407-414 - [c12]Mikiko Sato, Yuji Sato, Mitaro Namiki:
Acceleration experiment of genetic computations for sudoku solution on multi-core processors. GECCO (Companion) 2011: 823-824 - 2010
- [c11]Mikiko Sato, Yuji Sato, Mitaro Namiki:
Proposal of a multi-core processor from the viewpoint of evolutionary computation. IEEE Congress on Evolutionary Computation 2010: 1-8 - [c10]Mikiko Sato, Yuji Sato, Mitaro Namiki:
Proposal of a multi-core processor architecture for effective evolutionary computation. GECCO 2010: 1321-1322
2000 – 2009
- 2009
- [c9]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara:
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - 2006
- [c8]Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo:
A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915 - [c7]Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo:
Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924 - 2005
- [c6]Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453 - [c5]Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki:
Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460 - 2004
- [c4]Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323 - 2003
- [c3]Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615 - [c2]Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675 - [c1]Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki:
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
Coauthor Index
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