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2020 – today
- 2024
[j46]Alberto Bosio
, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola:
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs. J. Electron. Test. 40(2): 199-214 (2024)- [j45]Alberto Bosio, Ronald F. DeMara, Deliang Fan, Nima TaheriNejad:
Guest Editorial IEEE Transactions on Emerging Topics in Special Section on Emerging In-Memory Computing Architectures and Applications. IEEE Trans. Emerg. Top. Comput. 12(1): 4-6 (2024) - [c193]Cristiana Bolchini, Alberto Bosio:
Resilience of Deep Learning Applications: Where We are and Where We Want to Go. DATE 2024: 1 - [c192]Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux:
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE 2024: 1-6 - [c191]Taha Shahroodi, Raphael Cardoso, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui:
High-Performance Data Mapping for BNNs on PCM-Based Integrated Photonics. DATE 2024: 1-6 - [c190]Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. DDECS 2024: 19-24 - [c189]Marcello Traiola, Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio, Sepide Saeedi, Alessio Carpegna, Anil Bayram Gogebakan, Enrico Magliano, Alessandro Savino:
Approximate Fault-Tolerant Neural Network Systems. ETS 2024: 1-10 - [c188]Diamante Simone Crescenzo, Rafael Carrera Rodriguez, Riccardo Alidori, Florent Bruguier, Emanuele Valea, Pascal Benoit, Alberto Bosio:
Hardware Accelerator for FIPS 202 Hash Functions in Post-Quantum Ready SoCs. IOLTS 2024: 1-6 - [c187]Alberto Bosio, M. Gomes, Fabio Pavanello, A. Porsia, Annachiara Ruospo, Ernesto Sánchez, Elena I. Vatajelu:
Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks. LATS 2024: 1-10 - [c186]Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin:
Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. VLSI-SoC 2024: 1-4 - [c185]Sara Mannaa, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Ian O'Connor:
3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis. VLSI-SoC 2024: 1-4 - [c184]Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola:
Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS 2024: 1-11 - [i7]Taha Shahroodi, Raphael Cardoso, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui:
High-Performance Data Mapping for BNNs on PCM-based Integrated Photonics. CoRR abs/2401.17724 (2024) - [i6]Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. CoRR abs/2403.02946 (2024) - [i5]Mauricio Gomes de Queiroz, Paul Jiménez, Raphael Cardoso, Mateus Vidaletti Costa, Mohab Abdalla, Ian O'Connor, Alberto Bosio, Fabio Pavanello:
The Impact of Feature Representation on the Accuracy of Photonic Neural Networks. CoRR abs/2406.18757 (2024) - 2023
- [j44]Annachiara Ruospo, Ernesto Sánchez, Lucas Matana Luza, Luigi Dilillo, Marcello Traiola, Alberto Bosio:
A Survey on Deep Learning Resilience Assessment Methodologies. Computer 56(2): 57-66 (2023) - [j43]Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich:
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test 40(3): 5-7 (2023) - [j42]Alberto Bosio, Lara Dolecek, Alexandra Kourfali, Sri Parameswaran, Alessandro Savino:
Special Issue: "Approximation at the Edge". ACM Trans. Embed. Comput. Syst. 22(4): 72:1-72:4 (2023) - [c183]Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola:
Exploiting assertions mining and fault analysis to guide RTL-level approximation. DATE 2023: 1-2 - [c182]Taha Shahroodi, Raphael Cardoso, Mahdi Zahedi, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui:
Lightspeed Binary Neural Networks using Optical Phase-Change Materials. DATE 2023: 1-2 - [c181]Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio:
Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator. DDECS 2023: 181-186 - [c180]Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio:
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator. DFT 2023: 1-6 - [c179]Ali Piri, Salvatore Pappalardo, Salvatore Barone, Mario Barbareschi, Bastien Deveautour, Marcello Traiola, Ian O'Connor, Alberto Bosio:
Input-aware accuracy characterization for approximate circuits. DSN-W 2023: 179-182 - [c178]Rajendra Bishnoi, Sumit Diware, Anteneh Gebregiorgis, Simon Thomann, Sara Mannaa, Bastien Deveautour, Cédric Marchand, Alberto Bosio, Damien Deleruyelle, Ian O'Connor, Hussam Amrouch, Said Hamdioui:
Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. ICM 2023: 325-334 - [c177]Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio:
A Fault Injection Framework for AI Hardware Accelerators. LATS 2023: 1-6 - [c176]Cédric Marchand, Alban Nicolas, Paul-Antoine Matrangolo, David Navarro, Alberto Bosio, Ian O'Connor:
FeFET based Logic-in-Memory design methodologies, tools and open challenges. VLSI-SoC 2023: 1-6 - [c175]Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. VTS 2023: 1-10 - [c174]Fabio Pavanello, Elena-Ioana Vatajelu, Alberto Bosio, Thomas Van Vaerenbergh, Peter Bienstman, Benoît Charbonnier, Alessio Carpegna, Stefano Di Carlo, Alessandro Savino:
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies. VTS 2023: 1-10 - [e2]Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023. IEEE 2023, ISBN 979-8-3503-1500-4 [contents] - [i4]Fabio Pavanello, Elena-Ioana Vatajelu, Alberto Bosio, Thomas Van Vaerenbergh, Peter Bienstman, Benoît Charbonnier, Alessio Carpegna, Stefano Di Carlo, Alessandro Savino:
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies. CoRR abs/2305.01818 (2023) - [i3]Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. CoRR abs/2306.04645 (2023) - 2022
- [j41]Said Hamdioui, Elena I. Vatajelu, Alberto Bosio:
Guest Editorial: Computation-In-Memory (CIM): from Device to Applications. ACM J. Emerg. Technol. Comput. Syst. 18(2): 31:1-31:3 (2022) - [j40]Mario Barbareschi, Salvatore Barone, Alberto Bosio, Jie Han, Marcello Traiola:
A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(3): 50:1-50:25 (2022) - [j39]Lucas Matana Luza, Annachiara Ruospo, Daniel Söderström, Carlo Cazzaniga, Maria Kastriotou, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo:
Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks. IEEE Trans. Emerg. Top. Comput. 10(4): 1867-1882 (2022) - [c173]Ali Piri, Sepide Saeedi, Mario Barbareschi, Bastien Deveautour, Stefano Di Carlo, Ian O'Connor, Alessandro Savino, Marcello Traiola, Alberto Bosio:
Input-Aware Approximate Computing. AQTR 2022: 1-6 - [c172]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression. ASP-DAC 2022: 134-139 - [c171]Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena-Ioana Vatajelu:
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? DDECS 2022: 7-13 - [c170]Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola:
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. DDECS 2022: 38-43 - [c169]Annachiara Ruospo, Gabriele Gavarini, Ilaria Bragaglia, Marcello Traiola, Alberto Bosio, Ernesto Sánchez:
Selective Hardening of Critical Neurons in Deep Neural Networks. DDECS 2022: 136-141 - [c168]Alberto Bosio, Stefano Di Carlo, Maurizio Rebaudengo, Alessandro Savino:
Toward the hardening of real-time operating systems. DFT 2022: 1-6 - [c167]Alberto Bosio, Maurizio Rebaudengo, Alessandro Savino:
Reliability assessment of FreeRTOS in Embedded Systems. DSN (Supplements) 2022: 28-30 - [c166]Alberto Bosio, Bastien Deveautour, Ian O'Connor:
Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks. ISVLSI 2022: 326 - [c165]Alberto Bosio, Moreno Bragaglio, Samuele Germiniani, Samuele Mori, Graziano Pravadelli, Marcello Traiola:
Assertion-aware approximate computing design exploration on behavioral models. LATS 2022: 1-6 - [c164]Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar:
A Logic Cell Design and routing Methodology Specific to VNWFET. NEWCAS 2022: 460-464 - [p1]Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test and Reliability of Approximate Hardware. Approximate Computing 2022: 233-266 - [e1]Luca Cassano, Sreejit Chakravarty, Alberto Bosio:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022. IEEE 2022, ISBN 978-1-6654-5938-9 [contents] - [i2]Etienne Dupuis, Silviu-Ioan Filip, Olivier Sentieys, David Novo, Ian O'Connor, Alberto Bosio:
Approximations in Deep Learning. CoRR abs/2212.04297 (2022) - 2021
- [j38]Salvatore Barone, Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Multi-Objective Application-Driven Approximate Design Method. IEEE Access 9: 86975-86993 (2021) - [j37]Mario Barbareschi, Alberto Bosio, Lukás Sekanina, Claus Braun:
Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Gener. Comput. Syst. 124: 54-55 (2021) - [j36]Annachiara Ruospo, Ernesto Sánchez, Marcello Traiola, Ian O'Connor, Alberto Bosio:
Investigating data representation for efficient and reliable Convolutional Neural Networks. Microprocess. Microsystems 86: 104318 (2021) - [c163]Olivier Sentieys, Silviu-Ioan Filip, David Briand, David Novo, Etienne Dupuis, Ian O'Connor, Alberto Bosio:
AdequateDL: Approximating Deep Learning Accelerators. DDECS 2021: 37-40 - [c162]Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez, Luigi Dilillo:
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. DDECS 2021: 41-44 - [c161]Alessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio:
Efficient Neural Network Approximation via Bayesian Reasoning. DDECS 2021: 45-50 - [c160]Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola:
Emerging Technologies: Challenges and Opportunities for Logic Synthesis. DDECS 2021: 93-98 - [c159]Zoran Stamenkovic, Hassen Aziza, Ernesto Sánchez, Alberto Bosio:
Tutorial: Silicon Systems for Wireless LAN. DDECS 2021: 157-158 - [c158]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c157]Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD 2021: 1-9 - [c156]Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar:
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED 2021: 48-53 - [c155]Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alberto Bosio:
Approximate Computing for Safety-Critical Applications. LATS 2021: 1-3 - [c154]Annachiara Ruospo, Lucas Matana Luza, Alberto Bosio, Marcello Traiola, Luigi Dilillo, Ernesto Sánchez:
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks. LATS 2021: 1-5 - [c153]Emmanuel Casseau, Petr Dobiás, Oliver Sinnen, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alessandro Savino, Stefano Di Carlo, Maurizio Rebaudengo, Alberto Bosio:
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum. VTS 2021: 1-10 - [i1]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
Fast Exploration of Weight Sharing Opportunities for CNN Compression. CoRR abs/2102.01345 (2021) - 2020
- [j35]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE 108(12): 2178-2194 (2020) - [c152]Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP 2020: 157-164 - [c151]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Maximizing Yield for Approximate Integrated Circuits. DATE 2020: 810-815 - [c150]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression. DATE 2020: 1319-1322 - [c149]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing. DDECS 2020: 1-6 - [c148]Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo:
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. DFT 2020: 1-6 - [c147]Dario Mamone, Alberto Bosio, Alessandro Savino, Said Hamdioui, Maurizio Rebaudengo:
On the Analysis of Real-time Operating System Reliability in Embedded Systems. DFT 2020: 1-6 - [c146]Annachiara Ruospo, Angelo Balaara, Alberto Bosio, Ernesto Sánchez:
A Pipelined Multi-Level Fault Injector for Deep Neural Networks. DFT 2020: 1-6 - [c145]Annachiara Ruospo, Alberto Bosio, Alessandro Ianne, Ernesto Sánchez:
Evaluating Convolutional Neural Networks Reliability depending on their Data Representation. DSD 2020: 672-679 - [c144]Alberto Bosio, Ramon Canal, Stefano Di Carlo, Dimitris Gizopoulos, Alessandro Savino:
Cross-Layer Soft-Error Resilience Analysis of Computing Systems. DSN (Supplements) 2020: 79 - [c143]Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Lima, Said Hamdioui:
Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms. DTIS 2020: 1-2 - [c142]Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo:
Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. DTIS 2020: 1-6 - [c141]Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel:
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS 2020: 1-10 - [c140]Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar:
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS 2020: 1-2 - [c139]Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar:
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC 2020: 1-10
2010 – 2019
- 2019
- [j34]Maha Kooli, Giorgio Di Natale, Alberto Bosio:
Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems. J. Electron. Test. 35(2): 145-162 (2019) - [j33]Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection. J. Electron. Test. 35(3): 367-381 (2019) - [j32]Alberto Bosio, Mario Barbareschi:
Special Issue on Design, Technology, and Test of Integrated Circuits and Systems. J. Circuits Syst. Comput. 28(Supplement-1): 1902001:1-1902001:1 (2019) - [j31]Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo:
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. IEEE Trans. Computers 68(5): 765-783 (2019) - [c138]Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, Surya Nagarajan, Moritz Fieback, Said Hamdioui:
Rebooting Computing: The Challenges for Test and Reliability. DFT 2019: 8138-8143 - [c137]Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale:
Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS 2019: 1-10 - [c136]Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar:
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS 2019: 21-26 - [c135]Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková:
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC 2019: 1-4 - [c134]Alberto Bosio, Paolo Bernardi, Annachiara Ruospo, Ernesto Sánchez:
A Reliability Analysis of a Deep Neural Network. LATS 2019: 1-6 - [c133]Gennaro Severino Rodrigues, Juan Fonseca, Fabio Benevenuti, Fernanda Lima Kastensmidt, Alberto Bosio:
Exploiting approximate computing for low-cost fault tolerant architectures. SBCCI 2019: 3 - [c132]Alberto Bosio, Wilson-Javier Pérez-Holguín, Ernesto Sánchez:
Exploiting Approximate Computing to Increase System Lifetime. VLSI-SoC 2019: 311-316 - 2018
- [j30]Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena-Ioana Vatajelu:
Test and Reliability in Approximate Computing. J. Electron. Test. 34(4): 375-387 (2018) - [j29]Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Estimating dynamic power consumption for memristor-based CiM architecture. Microelectron. Reliab. 80: 241-248 (2018) - [j28]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray:
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6(2): 278-287 (2018) - [c131]Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio:
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs. ARC 2018: 647-658 - [c130]Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Alberto Bosio, Fernanda Lima Kastensmidt, Edison Pignaton de Freitas:
ARFT: An Approximative Redundant Technique for Fault Tolerance. DCIS 2018: 1-6 - [c129]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS 2018: 85-90 - [c128]Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio:
Synthesis of Finite State Machines on Memristor Crossbars. DDECS 2018: 107-112 - [c127]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT 2018: 1-6 - [c126]Marcello Traiola, Alessandro Savino, Mario Barbareschi, Stefano Di Carlo, Alberto Bosio:
Predicting the Impact of Functional Approximation: from Component- to Application-Level. IOLTS 2018: 61-64 - [c125]Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications. IOLTS 2018: 291-294 - [c124]Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard:
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC 2018: 1-8 - [c123]Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection. LATS 2018: 1-6 - [c122]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Testing approximate digital circuits: Challenges and opportunities. LATS 2018: 1-6 - [c121]Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo:
Special session: How approximate computing impacts verification, test and reliability. VTS 2018: 1 - 2017
- [j27]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017) - [j26]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26(8): 1740004:1-1740004:19 (2017) - [j25]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26(8): 1740007:1-1740007:18 (2017) - [j24]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13(1): 10-28 (2017) - [j23]Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres:
Computing reliability: On the differences between software testing and software fault injection techniques. Microprocess. Microsystems 50: 102-112 (2017) - [c120]Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards approximation during test of Integrated Circuits. DDECS 2017: 28-33 - [c119]Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Formal Design Space Exploration for memristor-based crossbar architecture. DDECS 2017: 145-150 - [c118]Mario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, Elena-Ioana Vatajelu:
Memristive devices: Technology, design automation and computing frontiers. DTIS 2017: 1-8 - [c117]G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi:
An effective fault-injection framework for memory reliability enhancement perspectives. DTIS 2017: 1-6 - [c116]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards digital circuit approximation by exploiting fault simulation. EWDTS 2017: 1-7 - [c115]Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle:
Reliability of computing systems: From flip flops to variables. IOLTS 2017: 196-198 - [c114]Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi:
Approximate computing: Design & test for integrated circuits. LATS 2017: 1 - 2016
- [j22]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016) - [j21]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot:
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25(3): 1640013:1-1640013:18 (2016) - [c113]Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
System-level reliability evaluation through cache-aware software-based fault injection. DDECS 2016: 9-14 - [c112]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective approach for functional test programs compaction. DDECS 2016: 119-124 - [c111]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A hybrid power modeling approach to enhance high-level power models. DDECS 2016: 151-156 - [c110]Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel:
Auto-adaptive ultra-low power IC. DTIS 2016: 1-6 - [c109]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2 - [c108]Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test of low power circuits: Issues and industrial practices. ICECS 2016: 524-527 - [c107]Maha Kooli, Giorgio Di Natale, Alberto Bosio:
Cache-aware reliability evaluation through LLVM-based analysis and fault injection. IOLTS 2016: 19-22 - [c106]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan:
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED 2016: 185-191 - [c105]Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio:
Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED 2016: 295-300 - [c104]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI 2016: 731-736 - [c103]Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale:
Cross-layer system reliability assessment framework for hardware faults. ITC 2016: 1-10 - [c102]Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini:
Faster-than-at-speed execution of functional programs: An experimental analysis. VLSI-SoC 2016: 1-6 - [c101]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC 2016: 1-6 - [c100]Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio:
XbarGen: A memristor based boolean logic synthesis tool. VLSI-SoC 2016: 1-6 - [c99]Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sánchez, Federico Venini:
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs. VLSI-SoC (Selected Papers) 2016: 130-151 - [c98]Juergen Alt, Paolo Bernardi, Alberto Bosio, Riccardo Cantoro, Hans G. Kerkhoff, Andreas Leininger, Wolfgang Molzer, Alessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, R. Strasser:
Thermal issues in test: An overview of the significant aspects and industrial practice. VTS 2016: 1-4 - [c97]Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio:
Cache- and register-aware system reliability evaluation based on data lifetime analysis. VTS 2016: 1-6 - 2015
- [j20]Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Gianfranco Politano, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo:
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview. Microprocess. Microsystems 39(8): 1204-1214 (2015) - [c96]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. DATE 2015: 1277-1280 - [c95]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot:
Design-for-Diagnosis Architecture for Power Switches. DDECS 2015: 43-48 - [c94]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective ATPG flow for Gate Delay Faults. DTIS 2015: 1-6 - [c93]Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres:
Software testing and software fault injection. DTIS 2015: 1-6 - [c92]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Scan-chain intra-cell defects grading. DTIS 2015: 1-6 - [c91]Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard:
An effective hybrid fault-tolerant architecture for pipelined cores. ETS 2015: 1-6 - [c90]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM 2015: 17-20 - [c89]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS 2015: 89-94 - [c88]Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c87]Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch:
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI 2015: 515-520 - 2014
- [j19]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j18]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. J. Electron. Test. 30(5): 541-555 (2014) - [j17]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine:
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30(5): 611-627 (2014) - [j16]Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2131-2144 (2014) - [j15]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay:
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2326-2335 (2014) - [c86]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC 2014: 544-549 - [c85]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray:
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS 2014: 312-317 - [c84]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Timing-aware ATPG for critical paths with multiple TSVs. DDECS 2014: 116-121 - [c83]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS 2014: 207-212 - [c82]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
Test and diagnosis of power switches. DDECS 2014: 213-218 - [c81]Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri:
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225 - [c80]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi:
An intra-cell defect grading tool. DDECS 2014: 298-301 - [c79]Luca Cassano, Alberto Bosio, Giorgio Di Natale:
A novel adaptive fault tolerant flip-flop architecture based on TMR. ETS 2014: 1-2 - [c78]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
iBoX - Jitter based Power Supply Noise sensor. ETS 2014: 1-2 - [c77]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI 2014: 226-231 - [c76]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi:
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW 2014: 69-72 - [c75]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS 2014: 1-6 - 2013
- [j14]Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard:
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. 9(2): 253-263 (2013) - [j13]Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 306-319 (2013) - [j12]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 958-970 (2013) - [c74]Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium 2013: 109-114 - [c73]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447 - [c72]Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS 2013: 143-148 - [c71]Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS 2013: 39-44 - [c70]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
Computing detection probability of delay defects in signal line tsvs. ETS 2013: 1-6 - [c69]Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS 2013: 1-6 - [c68]Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS 2013: 145-150 - [c67]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray:
Effect-cause intra-cell diagnosis at transistor level. ISQED 2013: 460-467 - [c66]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126 - [c65]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC 2013: 1-10 - [c64]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné:
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI 2013: 75-80 - [c63]Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS 2013: 1-4 - [c62]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS 2013: 1-6 - 2012
- [j11]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. J. Electron. Test. 28(2): 215-228 (2012) - [j10]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28(3): 317-329 (2012) - [j9]Alessandro Savino, Stefano Di Carlo, Gianfranco Politano, Alfredo Benso, Alberto Bosio, Giorgio Di Natale:
Statistical Reliability Estimation of Microprocessor-Based Systems. IEEE Trans. Computers 61(11): 1521-1534 (2012) - [c61]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium 2012: 125-130 - [c60]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot:
Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium 2012: 161-166 - [c59]Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka:
Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium 2012: 167-172 - [c58]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel:
Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium 2012: 221-226 - [c57]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 - [c56]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS 2012: 1 - [c55]Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Through-Silicon-Via resistive-open defect analysis. ETS 2012: 1 - [c54]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Defect analysis in power mode control logic of low-power SRAMs. ETS 2012: 1 - [c53]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné:
Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS 2012: 121-122 - [c52]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC 2012: 1-10 - [c51]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich:
A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55 - [c50]Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Advanced test methods for SRAMs. VTS 2012: 300-301 - 2011
- [c49]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c48]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 - [c47]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 - [c46]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen:
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 - [c45]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 - [c44]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 - [c43]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 - [c42]Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch:
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT 2011: 226-232 - [c41]Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 - [c40]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda:
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS 2011: 153-158 - [c39]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 - 2010
- [j8]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6(2): 359-374 (2010) - [j7]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010) - [c38]Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo:
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 - [c37]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 - [c36]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 - [c35]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 - [c34]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An Exact and Efficient Critical Path Tracing Algorithm. DELTA 2010: 164-169 - [c33]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 - [c32]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. ETS 2010: 81-86 - [c31]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS 2010: 132-137 - [c30]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Setting test conditions for improving SRAM reliability. ETS 2010: 257 - [c29]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? ITC 2010: 805 - [c28]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 - [c27]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80
2000 – 2009
- 2009
- [j6]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Paolo Prinetto:
Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. IEEE Des. Test Comput. 26(3): 16-24 (2009) - [j5]Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3(6): 581-592 (2009) - [j4]Alberto Bosio, Giovanni Righini:
A dynamic programming algorithm for the single-machine scheduling problem with release dates and deteriorating processing times. Math. Methods Oper. Res. 69(2): 271-280 (2009) - [c26]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 - [c25]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS 2009: 50-55 - [c24]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 - [c23]Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259 - [c22]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard:
NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 - 2008
- [j3]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
March Test Generation Revealed. IEEE Trans. Computers 57(12): 1704-1713 (2008) - [c21]Alberto Bosio, Giorgio Di Natale:
LIFTING: A Flexible Open-Source Fault Simulator. ATS 2008: 35-40 - [c20]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi:
SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325 - [c19]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 - [c18]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 - [c17]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 - [c16]Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand:
A Modular Memory BIST for Optimized Memory Repair. IOLTS 2008: 171-172 - [c15]Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 - [c14]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 - 2007
- [j2]Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs. IET Comput. Digit. Tech. 1(3): 237-245 (2007) - [c13]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Fast Bridging Fault Diagnosis using Logic Information. ATS 2007: 33-38 - [c12]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 - [c11]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani:
A Functional Verification Based Fault Injection Environment. DFT 2007: 114-122 - [c10]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
DERRIC: A Tool for Unified Logic Diagnosis. ETS 2007: 13-20 - [c9]Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Alberto Bosio:
Automating the IEEE std.1500 compliance verification for embedded cores. HLDVT 2007: 171-178 - 2006
- [j1]Alberto Bosio, Giovanni Righini:
A dynamic programming algorithm for the single-machine scheduling problem with deteriorating processing times. Electron. Notes Discret. Math. 25: 139-142 (2006) - [c8]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Memory Fault Simulator for Static-Linked Faults. ATS 2006: 31-36 - [c7]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
ATPG for Dynamic Burn-In Test in Full-Scan Circuits. ATS 2006: 75-82 - [c6]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Automatic march tests generations for static linked faults in SRAMs. DATE 2006: 1258-1263 - [c5]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. DDECS 2006: 157-158 - [c4]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Automatic March Tests Generation for Multi-Port SRAMs. DELTA 2006: 385-392 - [c3]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
A 22n March Test for Realistic Static Linked Faults in SRAMs. ETS 2006: 49-54 - 2005
- [c2]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Automatic March tests generation for static and dynamic faults in SRAMs. ETS 2005: 122-127 - [c1]Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
March AB, March AB1: new March tests for unlinked dynamic memory faults. ITC 2005: 8
Coauthor Index
[j44] [j39] [c162] [c154] [c148] [c142] [j21] [c106] [c96] [c95] [c94] [c92] [c91] [c87] [j19] [j18] [j17] [j16] [j15] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c78] [c77] [c76] [c75] [j14] [j13] [j12] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c65] [c64] [c63] [c62] [j11] [j10] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c41] [c40] [c39] [j8] [c38] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c24] [c22] [c15]
[p1] [c158] [c156] [j35] [c151] [c141] [c140] [c139] [c136] [j28] [c129] [c127] [c124] [c122] [j27] [j26] [j25] [j24] [c120] [c117] [c116] [c114] [j22] [j21] [c112] [c111] [c110] [c109] [c108] [c106] [c104] [c101] [c96] [c95] [c94] [c92] [c91] [c90] [c89] [c88] [c87] [j19] [j18] [j17] [j16] [j15] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c78] [c77] [c76] [c75] [j14] [j13] [j12] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [j11] [j10] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [j8] [j7] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [j5] [c26] [c25] [c24] [c23] [c22] [c20] [c19] [c18] [c17] [c15] [c14] [c13] [c12] [c10]
[j22] [c87] [j19] [j18] [c83] [c77] [c72] [c68] [c64] [c63] [j11] [j10] [c50] [c48] [c47] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [j8] [j7] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [j5] [c26] [c25] [c24] [c23] [c22] [c20] [c19] [c18] [c17] [c15] [c14] [c13] [c12] [c10]
Aida Todri
aka: Aida Todri-Sanial
aka: Aida Todri-Sanial
Elena I. Vatajelu
aka: Elena-Ioana Vatajelu
aka: Elena-Ioana Vatajelu
[p1] [c158] [c156] [j35] [c151] [c141] [c140] [c139] [c136] [j28] [c129] [c127] [c124] [c122] [j27] [j26] [j25] [j24] [c120] [c117] [c116] [c114] [j22] [j21] [c112] [c111] [c110] [c109] [c108] [c106] [c105] [c104] [c101] [c96] [c95] [c94] [c92] [c91] [c90] [c89] [c88] [c87] [j19] [j18] [j17] [j16] [j15] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c78] [c77] [c76] [c75] [j13] [j12] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [j11] [j10] [c61] [c60] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c41] [c40] [c39] [j8] [j7] [c38] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [j5] [c26] [c24] [c23] [c22] [c19] [c18] [c17] [c15] [c14] [c13] [c12] [c10]
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