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2000 – 2009
- 2005
[c28]Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy
, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen:
An Efficient Sequential SAT Solver With Improved Search Strategies. DATE 2005: 1102-1107- 2004
- [j8]Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen:
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Des. Test Comput. 21(2): 111-120 (2004) - 2002
- [c27]Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154 - 2001
- [j7]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001) - 2000
- [j6]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer:
AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000)
1990 – 1999
- 1999
- [j5]Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska:
Logic synthesis for engineering change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 282-292 (1999) - [j4]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1376-1384 (1999) - 1998
- [j3]Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 852-861 (1998) - [c26]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu:
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637 - 1997
- [c25]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC 1997: 455-460 - [c24]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng:
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981 - [c23]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
Incremental logic rectification. VTS 1997: 143-149 - 1996
- [c22]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee:
Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164 - [c21]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
Error Correction Based on Verification Techniques. DAC 1996: 258-261 - [c20]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee:
Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC 1996: 334-339 - [c19]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277- - [c18]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee:
A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72 - [c17]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser:
An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874 - 1995
- [c16]Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Logic rectification and synthesis for engineering change. ASP-DAC 1995 - [c15]Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Logic Synthesis for Engineering Change. DAC 1995: 647-652 - [c14]Anmol Mathur, Kuang-Chien Chen, C. L. Liu:
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA 1995: 118-124 - [c13]Anmol Mathur, Kuang-Chien Chen, C. L. Liu:
Re-engineering of timing constrained placements for regular architectures. ICCAD 1995: 485-490 - [c12]Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design methodology. ICCAD 1995: 528-533 - 1994
- [j2]Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen:
LUT-based FPGA technology mapping under arbitrary net-delay models. Comput. Graph. 18(4): 507-516 (1994) - 1993
- [c11]Tong Gao, Chung Laung (Dave) Liu, Kuang-Chien Chen:
A performance driven hierarchical partitioning placement algorithm. EURO-DAC 1993: 33-38 - [c10]Kuang-Chien Chen:
Boolean matching based on Boolean unification. EURO-DAC 1993: 346-351 - 1992
- [j1]Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar:
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. 9(3): 7-20 (1992) - [c9]Kuang-Chien Chen, Masahiro Fujita:
Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC 1992: 443-448 - [c8]Kuang-Chien Chen, Jason Cong:
Maximal reduction of lookup-table based FPGAs. EURO-DAC 1992: 224-229 - [c7]Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen:
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158 - 1991
- [b1]Kuang-Chien Chen:
Logic synthesis and optimization algorithms. University of Illinois Urbana-Champaign, USA, 1991 - [c6]Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita:
A Resynthesis Approach for Network Optimization. DAC 1991: 458-463 - [c5]Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen:
Application of Boolean Unification to Combinational Logic Synthesis. ICCAD 1991: 510-513 - [c4]Kuang-Chien Chen, Masahiro Fujita:
Concurrent Resynthesis for Network Optimization. ICCD 1991: 44-48 - 1990
- [c3]Kuang-Chien Chen, Saburo Muroga:
Timing Optimization for Multi-Level Combinational Networks. DAC 1990: 339-344
1980 – 1989
- 1989
- [c2]Kuang-Chien Chen, Saburo Muroga:
SYLON-DREAM: a multi-level network synthesizer. ICCAD 1989: 552-555 - 1988
- [c1]Kuang-Chien Chen, Saburo Muroga:
Input assignment algorithm for decoded-PLAs with multi-input decoders. ICCAD 1988: 474-477
Coauthor Index
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