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ORCIDHiroaki Katsurai
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2020 – today
- 2022
[c8]Takahiko Shindo, Masahiro Nada, Hiroaki Katsurai, Shigeru Kanazawa, Mingchen Chen, Yasuhiko Nakanishi, Atsushi Kanda, Koichi Hadama, Hirotaka Nakamura:
High-power SOA integrated EADFB laser and high-sensitivity burst-mode APD receiver toward 10G- and 25G-class long reach PON. OECC/PSC 2022: 1-3- 2021
- [j5]Masahiro Nada, Mingchen Chen, Hiroaki Katsurai, Yasuhiko Nakanishi, Toshihide Yoshimatsu, Atsushi Kanda, Hirotaka Nakamura, Kimikazu Sano:
Practically implementable high-sensitivity 10-Gbit/s avalanche photodiode using inverted p-down design. IEICE Electron. Express 18(11): 20210142 (2021) - 2020
- [c7]Hiroaki Katsurai, Yasuhiko Nakanishi, Atsushi Kanda, Toshihide Yoshimatsu, Shigeru Kanazawa, Masahiro Nada, Hirotaka Nakamura, Kimikazu Sano:
A 25G Burst-mode Receiver with -27.7-dBm Sensitivity and 150-ns Response-Time for 50G-EPON Systems. ECOC 2020: 1-3
2010 – 2019
- 2018
- [c6]Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Shinsuke Nakano, Hiroaki Katsurai, Takuro Fujii, Hidetaka Nishi, Takaaki Kakitsuka, Koichi Hasebe, Kota Shikama, Yuko Kawajiri, Atsushi Aratake, Hideyuki Nosaka, Hiroshi Fukuda, Shinji Matsuo:
A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si. OFC 2018: 1-3 - [c5]Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue
, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka:
A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS. VLSI-DAT 2018: 1-4 - 2015
- [j4]Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera:
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1288-1295 (2015) - 2014
- [c4]Shinsuke Nakano, Hiroaki Katsurai, Minoru Togashi, Hiroshi Koizumi, Masafumi Nogawa:
20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters. ISCAS 2014: 2696-2699 - [c3]Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai:
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS 2014: 2704-2707 - 2011
- [j3]Hiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, Tsugumichi Shibata:
An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System. IEICE Trans. Electron. 94-C(4): 582-588 (2011) - 2010
- [j2]Akio Yamamoto, Hiroaki Katsurai, Toshiro Higuchi:
DC-Operated Electrostatic Impact Drive Actuator. Adv. Robotics 24(10): 1441-1459 (2010)
2000 – 2009
- 2009
- [c2]Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto:
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. ISSCC 2009: 104-105 - 2008
- [j1]Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo:
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC. IEEE J. Solid State Circuits 43(12): 2921-2928 (2008) - [c1]Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo:
A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC. ISSCC 2008: 226-227
Coauthor Index
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