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ORCIDJien-Chung Lo
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2000 – 2009
- 2006
[j23]Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi:
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). IEEE Trans. Computers 55(2): 97-98 (2006)- [c25]Chuen-Song Chen, Jien-Chung Lo, Tian Xia:
Equivalent IDDQ Tests for Systems with Regulated Power Supply. DFT 2006: 291-299 - [c24]Chuen-Song Chen, Jien-Chung Lo, Tian Xia:
An indirect current sensing technique for IDDQ and IDDT tests. ACM Great Lakes Symposium on VLSI 2006: 235-240 - 2005
- [j22]Tian Xia, Jien-Chung Lo:
On-chip short-time interval measurement system for high-speed signal timing characterization. J. Syst. Archit. 51(4): 265-276 (2005) - [c23]Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara:
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. DFT 2005: 120-130 - 2004
- [j21]Seok-Bum Ko
, Jien-Chung Lo:
Efficient Realization of Parity Prediction Functions in FPGAs. J. Electron. Test. 20(5): 489-499 (2004) - [c22]Tian Xia, Peilin Song, Keith A. Jenkins, Jien-Chung Lo:
Delay chain based programmable jitter generator. ETS 2004: 16-21 - 2003
- [j20]Tian Xia, Jien-Chung Lo:
Time-to-voltage converter for on-chip jitter measurement. IEEE Trans. Instrum. Meas. 52(6): 1738-1748 (2003) - [c21]Tian Xia, Jien-Chung Lo:
On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. Asian Test Symposium 2003: 326-331 - [c20]Seok-Bum Ko, Jien-Chung Lo:
A Novel Technology Mapping Method for AND/XOR Expressions. ISMVL 2003: 133-138 - 2002
- [j19]Seok-Bum Ko, Yu-Yau Guo, Jien-Chung Lo:
Studies of the SEMATECH IDDq test data. J. Syst. Archit. 47(10): 831-846 (2002) - [j18]Jien-Chung Lo:
Analysis of a BICS-Only Concurrent Error Detection Method. IEEE Trans. Computers 51(3): 241-253 (2002) - [c19]Tian Xia, Jien-Chung Lo:
On-Chip Jitter Measurement for Phase Locked Loops. DFT 2002: 399-407 - [c18]Seok-Bum Ko, Jien-Chung Lo:
Efficient Decomposition Techniques for FPGAs. HiPC 2002: 630-642 - 2001
- [j17]Jien-Chung Lo, William D. Armitage, Corbet S. Johnson:
Using Atomic Force Microscopy for Deep-Submicron Failure Analysis. IEEE Des. Test Comput. 18(1): 10-18 (2001) - [c17]Seok-Bum Ko, Tian Xia, Jien-Chung Lo:
Efficient Parity Prediction in FPGA. DFT 2001: 176-181 - 2000
- [j16]Cecilia Metra, Jien-Chung Lo:
Intermediacy Prediction for High Speed Berger Code Checkers. J. Electron. Test. 16(6): 607-615 (2000) - [j15]Augustus K. Uht, Jien-Chung Lo, Ying Sun, James C. Daly, James Kowalski:
Building Real Computer Systems. IEEE Micro 20(3): 48-56 (2000) - [c16]Shengli Li, Kai Zhang, Jien-Chung Lo:
The 2nd Order Analysis of IDDQ Test Data. DFT 2000: 376-
1990 – 1999
- 1999
- [c15]William D. Armitage, Jien-Chung Lo:
Erasure Error Correction with Hardware Detection. DFT 1999: 293-301 - 1998
- [j14]Jien-Chung Lo:
Online Current Testing. IEEE Des. Test Comput. 15(4): 49-56 (1998) - [j13]Jien-Chung Lo:
Correction to "A Fast Binary Adder with Conditional Carry Generation" IEEE Transaction on Computers 46(2) 248-253 (1997). IEEE Trans. Computers 47(12): 1425 (1998) - [j12]Jien-Chung Lo:
A Case Study of Self-Checking Circuits Reliability. VLSI Design 5(4): 373-383 (1998) - [c14]Yu-Yau Guo, Jien-Chung Lo:
Challenges of Built-In Current Sensor Designs. DFT 1998: 192- - [c13]Jien-Chung Lo:
Highly Reliable Systems with Differential Built-In Current Sensors. DFT 1998: 261-269 - 1997
- [j11]Jien-Chung Lo:
A Fast Binary Adder with Conditional Carry Generation. IEEE Trans. Computers 46(2): 248-253 (1997) - [c12]Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra:
Fast and area-time efficient Berger code checkers. DFT 1997: 110-118 - 1996
- [j10]Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao:
Berger Check Prediction for Array Multipliers and Array Dividers. IEEE Trans. Computers 45(3): 383 (1996) - [j9]Jien-Chung Lo, Eiji Fujiwara:
Probability to Achieve TSC Goal. IEEE Trans. Computers 45(4): 450-460 (1996) - [j8]Jien-Chung Lo:
A Hyper Optimal Encoding Scheme for Self-Checking Circuits. IEEE Trans. Computers 45(9): 1022-1030 (1996) - [c11]Peilin Song, Jien-Chung Lo:
Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library. DFT 1996: 114-123 - [c10]Jien-Chung Lo, Masato Kitakami, Eiji Fujiwara:
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. DFT 1996: 286-294 - 1995
- [j7]Jien-Chung Lo, James C. Daly, Michael Nicolaidis:
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1402-1407 (1995) - [c9]Jien-Chung Lo:
Single fault masking logic designs with error correcting codes. DFT 1995: 296- - 1994
- [j6]Jien-Chung Lo, Shih-Yao Sun, James C. Daly:
A concurrent error detection IC in 2-μm static CMOS logic. IEEE J. Solid State Circuits 29(5): 580-584 (1994) - [j5]Jien-Chung Lo:
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. IEEE Trans. Computers 43(4): 400-412 (1994) - 1993
- [j4]Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao:
Berger Check Prediction for Array Multipliers and Array Dividers. IEEE Trans. Computers 42(7): 892-896 (1993) - [j3]T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo:
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. IEEE Trans. Computers 42(8): 1020-1024 (1993) - [c8]Jien-Chung Lo, Eiji Fujiwara:
A Probabilistic Measurement for Totally Self-Checking Circuits. DFT 1993: 263-270 - [c7]Jien-Chung Lo:
Fault-Tolerant Content Addressable Memory. ICCD 1993: 193-196 - 1992
- [j2]Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis:
An SFS Berger check prediction ALU and its application to self-checking processor designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 525-540 (1992) - [c6]Jien-Chung Lo, James C. Daly, Michael Nicolaidis:
Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing. FTCS 1992: 104-111 - [c5]Jien-Chung Lo:
Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. ICCD 1992: 110-113 - [c4]Tung-Li Shen, James C. Daly, Jien-Chung Lo:
On-chip current sensing circuit for CMOS VLSI. VTS 1992: 309-314 - 1991
- [c3]Hungshih Chang, Jien-Chung Lo:
A new protocol for efficient bandwidth distribution in integrated service networks. LCN 1991: 467-472 - 1990
- [j1]Jien-Chung Lo, Suchai Thanawastien:
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. IEEE Trans. Computers 39(3): 387-393 (1990)
1980 – 1989
- 1989
- [c2]Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao:
Concurrent error detection in arithmetic and logical operations using Berger codes. IEEE Symposium on Computer Arithmetic 1989: 233-240 - 1988
- [c1]Jien-Chung Lo, Suchai Thanawastien:
The design of fast totally self-checking Berger code checkers based on Berger code partitioning. FTCS 1988: 226-231
Coauthor Index
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