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2020 – today
- 2024
[j44]Shailja Pandey
, Sayam Sethi, Preeti Ranjan Panda:
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2263-2276 (2024)- [j43]Aritra Bagchi, Dinesh Joshi, Preeti Ranjan Panda:
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration. ACM Trans. Embed. Comput. Syst. 23(1): 12:1-12:30 (2024) - [j42]Shailja Pandey, Preeti Ranjan Panda:
NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance. ACM Trans. Embed. Comput. Syst. 23(6): 96:1-96:30 (2024) - [j41]Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda:
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. ACM Trans. Design Autom. Electr. Syst. 29(1): 19:1-19:35 (2024) - 2023
- [j40]Preeti Ranjan Panda:
Editorial. IEEE Embed. Syst. Lett. 15(4): 169 (2023) - [j39]Garima Modi, Aritra Bagchi, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda:
CABARRE: Request Response Arbitration for Shared Cache Management. ACM Trans. Embed. Comput. Syst. 22(5s): 130:1-130:24 (2023) - [j38]Lokesh Siddhu, Aritra Bagchi, Rajesh Kedia, Isaar Ahmad, Shailja Pandey, Preeti Ranjan Panda:
Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure. ACM Trans. Embed. Comput. Syst. 22(6): 104:1-104:27 (2023) - [j37]Divya Praneetha Ravipati, Victor M. van Santen, Sami Salamin, Hussam Amrouch, Preeti Ranjan Panda:
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1280-1293 (2023) - [c69]Preeti Ranjan Panda, Shailja Pandey:
Education Abstract: Thermal Challenges and Mitigation in 3D DRAM. CODES+ISSS 2023: 40-41 - 2022
- [j36]Preeti Ranjan Panda:
Editorial. IEEE Embed. Syst. Lett. 14(1): 1-2 (2022) - [j35]Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda:
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. ACM Trans. Archit. Code Optim. 19(3): 44:1-44:25 (2022) - [j34]Shailja Pandey, Preeti Ranjan Panda:
NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3602-3613 (2022) - [j33]Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Jörg Henkel, Preeti Ranjan Panda, Hussam Amrouch:
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 339-352 (2022) - [c68]Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda:
CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance. DATE 2022: 1377-1382 - 2021
- [j32]Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda:
A Survey of Cache Simulators. ACM Comput. Surv. 53(1): 19:1-19:32 (2021) - [j31]Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda:
Leakage-Aware Dynamic Thermal Management of 3D Memories. ACM Trans. Design Autom. Electr. Syst. 26(2): 12:1-12:31 (2021) - [e1]Ümit Y. Ogras, Preeti Ranjan Panda:
CASES '21: Proceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Virtual Event, October 8 - 15, 2021. ACM 2021, ISBN 978-1-4503-8378-3 [contents] - [i2]Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda:
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. CoRR abs/2109.12405 (2021) - 2020
- [j30]Preeti Ranjan Panda:
Editorial-December 2020. IEEE Embed. Syst. Lett. 12(4): 103-104 (2020) - [j29]Neetu Jindal, Shubhani Gupta, Divya Praneetha Ravipati, Preeti Ranjan Panda, Smruti R. Sarangi:
Enhancing Network-on-Chip Performance by Reusing Trace Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 922-935 (2020) - [j28]Sakshi Tiwari, Shreshth Tuli, Isaar Ahmad, Ayushi Agarwal, Preeti Ranjan Panda, Sreenivas Subramoney:
REAL: REquest Arbitration in Last Level Caches. ACM Trans. Embed. Comput. Syst. 18(6): 115:1-115:24 (2020)
2010 – 2019
- 2019
- [j27]Lokesh Siddhu, Preeti Ranjan Panda:
PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor. ACM Trans. Embed. Comput. Syst. 18(5s): 64:1-64:22 (2019) - [j26]Hadi Brais, Preeti Ranjan Panda:
Alleria: An Advanced Memory Access Profiling Framework. ACM Trans. Embed. Comput. Syst. 18(5s): 81:1-81:22 (2019) - [c67]Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli:
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring. DAC 2019: 99 - [c66]Lokesh Siddhu, Preeti Ranjan Panda:
FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories. DATE 2019: 272-275 - [c65]Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra:
Techniques for Debug of Low Power SoCs. MTV 2019: 45-49 - [c64]Vivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri:
Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. VLSID 2019: 281-286 - 2018
- [j25]Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi:
Reusing Trace Buffers as Victim Caches. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1699-1712 (2018) - [c63]Preeti Ranjan Panda, Namita Sharma, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh:
Exploration of Loop Unroll Factors in High Level Synthesis. VLSID 2018: 465-466 - 2017
- [j24]Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network. ACM Trans. Archit. Code Optim. 14(4): 32:1-32:25 (2017) - [j23]Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar:
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1881-1894 (2017) - [c62]Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi:
Reusing trace buffers to enhance cache performance. DATE 2017: 572-577 - [c61]Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. DATE 2017: 800-805 - [p1]Preeti Ranjan Panda:
Memory Architectures. Handbook of Hardware/Software Codesign 2017: 411-441 - 2016
- [j22]Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Min Li, Prashant Agrawal:
Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD. ACM Trans. Embed. Comput. Syst. 15(1): 18:1-18:23 (2016) - [j21]Iason Filippopoulos, Namita Sharma, Francky Catthoor, Per Gunnar Kjeldsberg, Preeti Ranjan Panda:
Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures. ACM Trans. Embed. Comput. Syst. 15(3): 59:1-59:23 (2016) - [j20]Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen:
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures. ACM Trans. Design Autom. Electr. Syst. 22(1): 12:1-12:25 (2016) - [j19]Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda:
Area-Aware Cache Update Trackers for Postsilicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1794-1807 (2016) - [c60]Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi:
Extending trace history through tapered summaries in post-silicon validation. ASP-DAC 2016: 737-742 - [c59]Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. DATE 2016: 253-256 - [c58]Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi:
A Generic Implementation of Barriers Using Optical Interconnects. VLSID 2016: 349-354 - 2015
- [j18]Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa:
Array Interleaving - An Energy-Efficient Data Layout Transformation. ACM Trans. Design Autom. Electr. Syst. 20(3): 44:1-44:26 (2015) - [c57]Namita Sharma, Preeti Ranjan Panda, Francky Catthoor:
Energy efficient FFT implementation through stage skipping and merging. CODES+ISSS 2015: 153-162 - [c56]Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma:
Power Optimization Techniques for DDR3 SDRAM. VLSID 2015: 310-315 - [i1]Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi:
Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects. CoRR abs/1510.00220 (2015) - 2014
- [j17]Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda:
Shared-port register file architecture for low-energy VLIW processors. ACM Trans. Archit. Code Optim. 11(1): 1:1-1:32 (2014) - [c55]Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan:
Array scalarization in high level synthesis. ASP-DAC 2014: 622-627 - [c54]Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan:
Energy optimization in Android applications through wakelock placement. DATE 2014: 1-4 - [c53]Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor:
Energy efficient data flow transformation for Givens Rotation based QR Decomposition. DATE 2014: 1-4 - [c52]Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N.:
High level energy modeling of controller logic in data caches. ACM Great Lakes Symposium on VLSI 2014: 45-50 - 2013
- [c51]Prasenjit Chakraborty, Preeti Ranjan Panda:
SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems. CASES 2013: 21:1-21:10 - [c50]Radu Marculescu, Preeti Ranjan Panda:
Message from the program co-chairs. CODES+ISSS 2013 - [c49]Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda:
Space sensitive cache dumping for post-silicon validation. DATE 2013: 497-502 - [c48]Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, Francky Catthoor:
Data memory optimization in LTE downlink. ICASSP 2013: 2610-2614 - [c47]Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan:
Power Supply Efficiency Aware Server Allocation in Data Centers. VLSI Design 2013: 233-238 - 2012
- [j16]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
Exploiting UML based validation for compliance checking of TLM 2 based models. Des. Autom. Embed. Syst. 16(2): 93-113 (2012) - [c46]Prasenjit Chakraborty, Preeti Ranjan Panda:
Integrating software caches with scratch pad memory. CASES 2012: 201-210 - [c45]Amit Kumar, Preeti Ranjan Panda, Smruti R. Sarangi:
Efficient on-line algorithm for maintaining k-cover of sparse bit-strings. FSTTCS 2012: 249-256 - 2011
- [j15]Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi:
Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60(4): 484-497 (2011) - [c44]Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar:
Exploiting temporal decoupling to accelerate trace-driven NoC emulation. CODES+ISSS 2011: 315-324 - [c43]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
A SysML Profile for Development and Early Validation of TLM 2.0 Models. ECMFA 2011: 299-311 - [c42]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
A UML based framework for efficient validation of TLM 2 models. FDL 2011: 1-8 - 2010
- [j14]Preeti Ranjan Panda, Rajendran Panda:
Guest Editorial: Special Issue on VLSI Design and Embedded Systems. Int. J. Parallel Program. 38(3-4): 183-184 (2010) - [c41]B. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda:
Rank based dynamic voltage and frequency scaling fortiled graphics processors. CODES+ISSS 2010: 3-12 - [c40]Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar:
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. CODES+ISSS 2010: 247-256 - [c39]Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan:
Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC 2010: 55-60 - [c38]Anshul Kumar, Preeti Ranjan Panda:
Front-End Design Flows for Systems on Chip: An Embedded Tutorial. VLSI Design 2010: 417-422
2000 – 2009
- 2009
- [j13]Rajendran Panda, Preeti Ranjan Panda:
A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. J. Low Power Electron. 5(3): 255-256 (2009) - [c37]Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Online cache state dumping for processor debug. DAC 2009: 358-363 - [c36]Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Cache aware compression for processor debug support. DATE 2009: 208-213 - [c35]Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda:
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE 2009: 1018-1023 - [c34]B. V. N. Silpa, Kumar S. S. Vemuri, Preeti Ranjan Panda:
Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. ISVC (1) 2009: 111-124 - 2008
- [j12]Preeti Ranjan Panda:
Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems. Int. J. Parallel Program. 36(1): 1-2 (2008) - [c33]Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda:
REWIRED - Register Write Inhibition by Resource Dedication. ASP-DAC 2008: 28-31 - [c32]B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran:
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ICCAD 2008: 559-564 - 2007
- [j11]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Int. J. Parallel Program. 35(6): 507-527 (2007) - [c31]Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda:
The impact of loop unrolling on controller delay in high level synthesis. DATE 2007: 391-396 - [c30]Rahul Jain, Preeti Ranjan Panda:
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. ISCAS 2007: 1377-1380 - [c29]Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda:
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. VLSI Design 2007: 233-238 - [c28]Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda:
Customization of Register File Banking Architecture for Low Power. VLSI Design 2007: 239-244 - [c27]Rahul Jain, Preeti Ranjan Panda:
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. VLSI Design 2007: 813-818 - 2006
- [c26]Preeti Ranjan Panda:
Abridged addressing: a low power memory addressing strategy. ASP-DAC 2006: 892-897 - [c25]Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda:
Rapid estimation of control delay from high-level specifications. DAC 2006: 455-458 - 2005
- [c24]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735 - [c23]Vikram Singh Saun, Preeti Ranjan Panda:
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. VLSI Design 2005: 280-285 - 2003
- [j10]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda:
Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 928-938 (2003) - [c22]Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran:
Specification and Design of Multi-Million Gate SOCs. VLSI Design 2003: 18-19 - 2002
- [c21]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda:
An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC 2002: 608-611 - [c20]Preeti Ranjan Panda, Nikil D. Dutt:
Memory Architectures for Embedded Systems-On-Chip. HiPC 2002: 647-662 - [c19]Preeti Ranjan Panda, Lakshmikantam Chitturi:
An energy-conscious algorithm for memory port allocation. ICCAD 2002: 572-576 - 2001
- [j9]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef:
Data Memory Organization and Optimizations in Application-Specific Systems. IEEE Des. Test Comput. 18(3): 56-68 (2001) - [j8]Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg:
Data and memory optimization techniques for embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(2): 149-206 (2001) - [c18]Preeti Ranjan Panda:
SystemC: A Modeling Platform Supporting Multiple Design Abstractions. ISSS 2001: 75-80 - [c17]Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda:
New Design Paradigms: What Needs to be Standardized?. ISSS 2001: 94 - [c16]Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli:
Cache-efficient memory layout of aggregate data structures. ISSS 2001: 101-106 - [c15]Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda:
Embedded Memories in System Design: Technology, Application, Design and Tools. VLSI Design 2001: 5-6 - 2000
- [j7]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Design Autom. Electr. Syst. 5(3): 682-704 (2000)
1990 – 1999
- 1999
- [j6]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48(2): 142-149 (1999) - [j5]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Local memory exploration and optimization in embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(1): 3-13 (1999) - [j4]Preeti Ranjan Panda, Nikil D. Dutt:
Low-power memory mapping through reducing address bus activity. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 309-320 (1999) - [c14]Preeti Ranjan Panda:
Memory bank customization and assignment in behavioral synthesis. ICCAD 1999: 477-481 - 1998
- [j3]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Incorporating DRAM access modes into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 96-109 (1998) - [c13]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Data Cache Sizing for Embedded Processor Applications. DATE 1998: 925-926 - 1997
- [j2]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Memory data organization for improved cache performance in embedded processor applications. ACM Trans. Design Autom. Electr. Syst. 2(4): 384-409 (1997) - [c12]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997: 7-11 - [c11]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Exploiting off-chip memory access modes in high-level synthesis. ICCAD 1997: 333-340 - [c10]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
A Data Alignment Technique for Improving Cache Performance. ICCD 1997: 587-592 - [c9]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
Improving cache Performance Through Tiling and Data Alignment. IRREGULAR 1997: 167-185 - [c8]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Architectural Exploration and Optimization of Local Memory in Embedded Systems. ISSS 1997: 90- - [c7]Preeti Ranjan Panda, Nikil D. Dutt:
Behavioral Array Mapping into Multiport Memories Targeting Low Power. VLSI Design 1997: 268-273 - 1996
- [c6]Preeti Ranjan Panda, Nikil D. Dutt:
Reducing Address Bus Transitions for Low Power Memory Mapping. ED&TC 1996: 63-71 - [c5]Preeti Ranjan Panda, Nikil D. Dutt:
Low-power mapping of behavioral arrays to multiple memories. ISLPED 1996: 289-292 - [c4]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Memory Organization for Improved Data Cache Performance in Embedded Processors. ISSS 1996: 90-95 - 1995
- [c3]Preeti Ranjan Panda, Nikil D. Dutt:
1995 high level synthesis design repository. ISSS 1995: 170-174 - 1993
- [j1]Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri:
Estimating the Complexity of Synthesized Designs from FSM Specifications. IEEE Des. Test Comput. 10(1): 30-35 (1993) - 1992
- [c2]Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri:
Estimating the Complexity of Synthesized Designs from FSM Specifications. VLSI Design 1992: 175-180 - 1991
- [c1]Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri:
A Flexible Scheme for State Assignment Based on Characteristics of the FSM. ICCAD 1991: 226-229
Coauthor Index
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