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ORCIDNam Sung Woo
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2000 – 2009
- 2006
[c15]Nam Sung Woo:
Promises and challenges of mobile embedded system: : an industry perspective. CODES+ISSS 2006: 3
1990 – 1999
- 1997
- [j8]Shih-Chieh Chang, Kwang-Ting Cheng
, Nam Sung Woo, Malgorzata Marek-Sadowska:
Postlayout logic restructuring using alternative wires. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 587-596 (1997) - 1995
- [c14]Nam Sung Woo:
Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs. FPGA 1995: 90-96 - 1994
- [j7]Nam Sung Woo, Alfred E. Dunlop, Wayne H. Wolf:
Codesign from Cospecification. Computer 27(1): 42-47 (1994) - [j6]Nam Sung Woo, Bruce F. Naylor:
Optimal Routing Algorithms for a Class of Cylindrical Banyan Multicomputers. J. Parallel Distributed Comput. 23(2): 239-245 (1994) - [c13]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska:
Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313 - 1993
- [j5]Dwight D. Hill, Nam Sung Woo:
The benefits of flexibility in lookup table-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 349-353 (1993) - [c12]Nam Sung Woo, Jaeseok Kim:
An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.. DAC 1993: 202-207 - 1992
- [c11]Dwight D. Hill, Barry K. Britton, William Oswald, Nam Sung Woo, Satwant Singh, Che-Tsung Chen, Bob Krambeck:
ORCA: A New Architecture for High-Performance FPLs. FPL 1992: 52-60 - [c10]James H. Aylor, Raul Camposano, Michael A. Schuette, Wayne H. Wolf, Nam Sung Woo:
The Future of Embedded System Design. ICCD 1992: 144-146 - 1991
- [c9]Nam Sung Woo:
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility. DAC 1991: 248-251 - 1990
- [c8]Nam Sung Woo:
A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System. DAC 1990: 505-510
1980 – 1989
- 1989
- [c7]Nam Sung Woo, Hyunchul Shin:
A Technology-adaptive Allocation of Functional Units and Connections. DAC 1989: 602-605 - [c6]Hyunchul Shin, Nam Sung Woo:
A cost function based optimization technique for scheduling in data path synthesis. ICCD 1989: 424-427 - 1987
- [c5]Nam Sung Woo, Ramautar Sharma:
An AND-OR Parallel Execution System for Logic Program Evaluation. ICPP 1987: 162-165 - 1986
- [j4]Nam Sung Woo, Richard A. O'Keefe:
A coment on "A hardware unification unit: design and analysis, ". SIGARCH Comput. Archit. News 14(1): 2-3 (1986) - [j3]Nam Sung Woo:
A reply to comments "a comment on 'a hardware unification unit: design and analysis, '". SIGARCH Comput. Archit. News 14(3): 2-4 (1986) - [c4]Nam Sung Woo, Kwang-Moo Choe:
Selecting the Backtrack Literal in the AND/OR Model. SLP 1986: 200-210 - 1985
- [j2]Nam Sung Woo, Ashok K. Agrawala:
A Symmetric Tree Structure Interconnection Network and its Message Traffic. IEEE Trans. Computers 34(8): 765-769 (1985) - [c3]Nam Sung Woo:
A Hardware Unification Unit: Design and Analysis. ISCA 1985: 198-205 - [c2]Nam Sung Woo:
The architecture of the hardware unification unit and an implementation. MICRO 1985: 89-98 - 1984
- [j1]Nam Sung Woo, Carl H. Smith, Ashok K. Agrawala:
A Proof of the Determinacy Property of the Data Flow Schema. Inf. Process. Lett. 19(1): 13-16 (1984) - 1983
- [c1]Nam Sung Woo, Ashok K. Agrawala:
The DC1 Flow Schema with the Data/Control-Driven Evaluation. ICPP 1983: 244-251
Coauthor Index
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