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ORCIDPaul Wielage
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2010 – 2019
- 2017
[c10]Fred Mostert, Daniël Schinkel, Wouter Groothedde, Lucien J. Breems, Remko van Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk-Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink:
5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter. ISSCC 2017: 86-87
2000 – 2009
- 2008
- [j3]Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers:
Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. IEEE J. Solid State Circuits 43(1): 192-201 (2008) - 2007
- [c9]Paul Wielage, Erik Jan Marinissen
, Michel Altheimer, Clemens Wouters:
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. DATE 2007: 853-858 - [c8]Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters:
Test quality analysis and improvement for an embedded asynchronous FIFO. DATE 2007: 859-864 - [c7]Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Marc J. M. Heijligers:
XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis. ISSCC 2007: 270-602 - 2005
- [j2]Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees Goossens:
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 4-17 (2005) - 2004
- [c6]Andrei Radulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, Paul Wielage:
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. DATE 2004: 878-883 - 2003
- [j1]Joep L. W. Kessels, Ad M. G. Peeters, Paul Wielage, Suk-Jin Kim:
Clock synchronization through handshake signalling. Microprocess. Microsystems 27(9): 447-460 (2003) - [c5]Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander:
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. DATE 2003: 10350-10355 - [p1]Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage:
Guaranteeing the Quality of Services in Networks on Chip. Networks on Chip 2003: 61-82 - 2002
- [c4]Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage:
Clock Synchronization through Handshake Signalling. ASYNC 2002: 59-68 - [c3]Kees Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen:
Networks on Silicon: Combining Best-Effort and Guaranteed Services. DATE 2002: 423-425 - [c2]Paul Wielage, Kees Goossens:
Networks on Silicon: Blessing or Nightmare? DSD 2002: 196-200 - 2001
- [c1]Richard P. Kleihorst, Anteneh A. Abbo, André van der Avoird, M. Op de Beeck, Leo Sevat, Paul Wielage, R. van Veen, H. van Herten:
Xetal: a low-power high-performance smart camera processor. ISCAS (5) 2001: 215-218
Coauthor Index
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