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ORCIDYannick Bonhomme
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2010 – 2019
- 2013
[j4]Valentin Gherman, Samuel Evain, Yannick Bonhomme:
Memory Reliability Improvement Based on Maximized Error-Correcting Codes. J. Electron. Test. 29(4): 601-608 (2013)- [c17]Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner
, Yannick Bonhomme, Valentin Gherman:
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. DATE 2013: 1077-1082 - 2012
- [c16]Valentin Gherman, Samuel Evain, Yannick Bonhomme:
Memory reliability improvements based on maximized error-correcting codes. ETS 2012: 1-6 - 2011
- [c15]Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme:
Error prediction based on concurrent self-test and reduced slack time. DATE 2011: 1626-1631 - [c14]Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme:
Generalized parity-check matrices for SEC-DED codes with fixed parity. IOLTS 2011: 198-201 - [c13]Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme:
Programmable extended SEC-DED codes for memory errors. VTS 2011: 140-145 - 2010
- [c12]Samuel Evain, Yannick Bonhomme, Valentin Gherman:
Programmable restricted SEC codes to mask permanent faults in semiconductor memories. IOLTS 2010: 147-153
2000 – 2009
- 2009
- [c11]Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme:
System-level hardware-based protection of memories against soft-errors. DATE 2009: 1222-1225 - [c10]Richard Buchmann, Mickael Cartron, Yannick Bonhomme:
Transaction-based modeling for large scale simulations of heterogeneous systems. SimuTools 2009: 33 - 2008
- [c9]Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme:
Power-On Controller for high lifetime wireless sensor nodes. WSAN 2008: 49-61 - 2006
- [j3]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22(1): 89-99 (2006) - 2005
- [j2]Patrick Girard, Yannick Bonhomme:
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. J. Low Power Electron. 1(1): 85-95 (2005) - 2004
- [j1]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20(6): 647-660 (2004) - [c8]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 - [c7]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 - [c6]Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard:
An efficient scan tree design for test time reduction. ETS 2004: 174-179 - 2003
- [c5]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493 - 2002
- [c4]Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449 - [c3]Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803 - 2001
- [c2]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258 - [c1]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89
Coauthor Index
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