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2020 – today
- 2024
[j3]Yuanlong Xiao
, Dongjoon Park, Zeyu Jason Niu, Aditya Hota, André DeHon:
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. ACM Trans. Reconfigurable Technol. Syst. 17(2): 21:1-21:28 (2024)- [i2]Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo:
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. CoRR abs/2410.13079 (2024) - 2023
- [j2]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023) - [c12]Dongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon:
Asymmetry in Butterfly Fat Tree FPGA NoC. ICFPT 2023: 227-231 - 2022
- [c11]Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon:
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. ASPLOS 2022: 933-945 - [c10]Yuanlong Xiao, André DeHon:
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. FPGA 2022: 155 - [c9]Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon:
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. FPL 2022: 70-78 - [c8]Dongjoon Park, Yuanlong Xiao, André DeHon:
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. FPT 2022: 1-10 - 2021
- [c7]Eric Micallef, Yuanlong Xiao, André DeHon:
HLS-Compatible, Embedded-Processor Stream Links. FCCM 2021: 214-218 - [i1]André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao:
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation. CoRR abs/2104.01929 (2021) - 2020
- [c6]Yuanlong Xiao, Syed Tousif Ahmed, André DeHon:
Fast Linking of Separately-Compiled FPGA Blocks without a NoC. FPT 2020: 196-205
2010 – 2019
- 2019
- [c5]Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai:
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. FPGA 2019: 121 - [c4]Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai:
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. ACM Great Lakes Symposium on VLSI 2019: 93-98 - [c3]Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon:
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. FPT 2019: 153-161 - 2018
- [c2]Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon:
Case for Fast FPGA Compilation Using Partial Reconfiguration. FPL 2018: 235-238 - 2016
- [j1]Yuanlong Xiao, Jian Wang, Jinmei Lai:
A universal automatic on-chip measurement of FPGA's internal setup and hold times. IEICE Electron. Express 13(23): 20160810 (2016) - 2015
- [c1]Yuanlong Xiao, Jian Wang, Jinmei Lai:
A power efficient current-mode differential driver for FPGAs. ASICON 2015: 1-4
Coauthor Index
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