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ORCIDManuel E. Acacio
Manuel E. Acacio Sanchez
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- affiliation: University of Murcia, Spain
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2020 – today
- 2024
[j46]Víctor Nicolás-Conesa
, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems 104: 104975 (2024)- [c72]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Alberto Ros:
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. MICRO 2024: 840-855 - 2023
- [j45]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna:
STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators. ACM J. Emerg. Technol. Comput. Syst. 19(4): 32:1-32:20 (2023) - [j44]Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras:
Speculative inter-thread store-to-load forwarding in SMT architectures. J. Parallel Distributed Comput. 173: 94-106 (2023) - [c71]Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros:
CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. PACT 2023: 1-13 - [c70]Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna:
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. ASPLOS (3) 2023: 252-265 - [i3]Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, Tushar Krishna:
Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. CoRR abs/2301.10852 (2023) - 2022
- [j43]Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean:
Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. 78(1): 919-944 (2022) - [j42]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 33(1): 1-13 (2022) - [c69]Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna:
Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators. IPDPS 2022: 571-582 - [c68]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP 2022: 157-164 - 2021
- [j41]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna:
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. IEEE Comput. Archit. Lett. 20(2): 122-125 (2021) - [c67]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna:
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. IISWC 2021: 201-213 - [c66]Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras:
ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. MICRO 2021: 1296-1308 - [c65]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna:
A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators. NOCS 2021: 1-8 - [i2]Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna:
A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators. CoRR abs/2103.07977 (2021) - 2020
- [j40]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. 145: 111-123 (2020) - [j39]Labiba Gillani Fahad, Syed Fahad Tahir, Waseem Shahzad, Mehdi Hassan, Hani Alquhayz, Rabia Hassan, Manuel E. Acacio Sanchez:
Ant Colony Optimization-Based Streaming Feature Selection: An Application to the Medical Image Diagnosis. Sci. Program. 2020: 1064934:1-1064934:10 (2020) - [j38]Brian Broll, Umesh Timalsina, Péter Völgyesi, Tamás Budavári, Ákos Lédeczi, Manuel E. Acacio Sanchez:
A Machine Learning Gateway for Scientific Workflow Design. Sci. Program. 2020: 8867380:1-8867380:15 (2020) - [j37]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 31(6): 1301-1315 (2020) - [i1]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna:
STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators. CoRR abs/2006.07137 (2020)
2010 – 2019
- 2019
- [j36]Manuel E. Acacio, Julio Sahuquillo:
Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems. Concurr. Comput. Pract. Exp. 31(21) (2019) - [j35]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio:
InsideNet: A tool for characterizing convolutional neural networks. Future Gener. Comput. Syst. 100: 298-315 (2019) - [j34]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio:
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30(11): 2608-2623 (2019) - [c64]Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio:
CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators. Euro-Par Workshops 2019: 720-724 - 2018
- [j33]José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio:
Photonic-based express coherence notifications for many-core CMPs. J. Parallel Distributed Comput. 113: 179-194 (2018) - [j32]Gregorio Bernabé, Manuel E. Acacio:
On the Parallelization of Stream Compaction on a Low-Cost SDC Cluster. Sci. Program. 2018: 2037272:1-2037272:10 (2018) - [j31]Gregorio Bernabé, Raúl Hernández, Manuel E. Acacio:
Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster. J. Supercomput. 74(4): 1765-1778 (2018) - [c63]Francisco Muñoz-Martínez, Manuel E. Acacio:
SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors. PDP 2018: 344-347 - 2017
- [j30]Juan M. Cebrian, Ricardo Fernández Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros:
A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. 29(2) (2017) - [j29]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. 73(10): 4428-4443 (2017) - [c62]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS 2017: 20:1-20:10 - 2016
- [j28]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. 72(2): 612-638 (2016) - [c61]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS 2016: 100-112 - 2015
- [j27]Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers 64(6): 1534-1547 (2015) - [j26]Alberto Ros, Manuel E. Acacio:
DASC-DIR: a low-overhead coherence directory for many-core processors. J. Supercomput. 71(3): 781-807 (2015) - [j25]Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio:
Fast and efficient commits for Lazy-Lazy hardware transactional memory. J. Supercomput. 71(12): 4305-4326 (2015) - [c60]Juan M. Cebrian, Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio:
Early Experiences with Separate Caches for Private and Shared Data. e-Science 2015: 572-579 - [r2]José L. Abellán, Juan Fernández, Manuel E. Acacio:
Efficient Hardware-Supported Synchronization Mechanisms for Manycores. Handbook on Data Centers 2015: 753-803 - [r1]J. Rubén Titos Gil, Manuel E. Acacio:
Hardware Approaches to Transactional Memory in Chip Multiprocessors. Handbook on Data Centers 2015: 805-835 - 2014
- [j24]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio:
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems. J. Supercomput. 68(2): 914-934 (2014) - [j23]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25(5): 1359-1369 (2014) - [c59]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) 2014: 254-265 - 2013
- [j22]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio:
On the design of energy-efficient hardware transactional memory systems. Concurr. Comput. Pract. Exp. 25(6): 862-880 (2013) - [j21]José L. Abellán, Juan Fernández, Manuel E. Acacio:
Design of an efficient communication infrastructure for highly contended locks in many-core CMPs. J. Parallel Distributed Comput. 73(7): 972-985 (2013) - [j20]J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(1): 59-71 (2013) - [j19]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(11): 2192-2201 (2013) - [c58]Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández:
Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory. ARCS 2013: 220-231 - [c57]Mario Lodde, José Flich, Manuel E. Acacio:
Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Euro-Par 2013: 178-190 - [c56]José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio:
Efficient Dir0B Cache Coherency for Many-Core CMPs. ICCS 2013: 2545-2548 - [c55]José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio:
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. ICSAMOS 2013: 237-244 - 2012
- [j18]J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. 8(4): 31:1-31:20 (2012) - [j17]Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61(5): 593-606 (2012) - [j16]José M. Cecilia, José L. Abellán, Juan Fernández, Manuel E. Acacio, José M. García, Manuel Ujaldon:
Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE. J. Supercomput. 62(2): 787-803 (2012) - [j15]José L. Abellán, Juan Fernández, Manuel E. Acacio:
Efficient Hardware Barrier Synchronization in Many-Core CMPs. IEEE Trans. Parallel Distributed Syst. 23(8): 1453-1466 (2012) - [c54]José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini:
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. DATE 2012: 491-496 - [c53]Mario Lodde, José Flich, Manuel E. Acacio:
Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Euro-Par 2012: 206-218 - [c52]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA 2012: 141-152 - [c51]Manuel E. Acacio, Javier Cuenca, Lorenzo Fernández Maimó, Ricardo Fernández Pascual, Joaquín Cervera, Domingo Giménez, M. Carmen Garrido, Juan A. Sánchez-Laguna, José Guillén, Juan Alejandro Palomino Benito, María-Eugenia Requena:
An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. IPDPS Workshops 2012: 1289-1294 - [c50]Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED 2012: 51-56 - [c49]Mario Lodde, José Flich, Manuel E. Acacio:
Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. NOCS 2012: 59-66 - [c48]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández:
Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. PDP 2012: 221-228 - [c47]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio:
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD 2012: 43-50 - 2011
- [c46]Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT 2011: 203-204 - [c45]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP 2011: 73-82 - [c44]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS 2011: 53-62 - [c43]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops 2011: 700-707 - [c42]José L. Abellán, Juan Fernández, Manuel E. Acacio:
GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs. IPDPS 2011: 893-905 - 2010
- [j14]Alberto Ros, Manuel E. Acacio, José M. García:
A scalable organization for distributed directories. J. Syst. Archit. 56(2-3): 77-87 (2010) - [j13]Antonio Flores, Manuel E. Acacio, Juan L. Aragón:
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs. J. Syst. Archit. 56(9): 429-441 (2010) - [j12]Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. IEEE Trans. Computers 59(1): 16-28 (2010) - [j11]José L. Abellán, Juan Fernández, Manuel E. Acacio:
Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats. J. Supercomput. 53(2): 247-268 (2010) - [j10]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. IEEE Trans. Parallel Distributed Syst. 21(8): 1117-1131 (2010) - [j9]Alberto Ros, Manuel E. Acacio, José M. García:
A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 21(12): 1779-1792 (2010) - [c41]José L. Abellán, Juan Fernández, Manuel E. Acacio:
Efficient and scalable barrier synchronization for many-core CMPs. Conf. Computing Frontiers 2010: 73-74 - [c40]Alberto Ros, Manuel E. Acacio:
Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops 2010: 87-97 - [c39]Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
EMC2: Extending Magny-Cours coherence for large-scale servers. HiPC 2010: 1-10 - [c38]José L. Abellán, Juan Fernández, Manuel E. Acacio:
A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs. ICPP 2010: 267-276 - [c37]Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. PDP 2010: 147-154 - [c36]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio:
Characterizing Energy Consumption in Hardware Transactional Memory Systems. SBAC-PAD 2010: 9-16
2000 – 2009
- 2009
- [c35]Alberto Ros, Manuel E. Acacio, José M. García:
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT 2009: 11-27 - [c34]Epifanio Gaona-Ramírez, Juan Fernández, Manuel E. Acacio:
Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades. Euro-Par 2009: 900-911 - [c33]Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García:
Distance-aware round-robin mapping for large NUCA caches. HiPC 2009: 79-88 - [c32]J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco:
Speculation-based conflict resolution in hardware transactional memory. IPDPS 2009: 1-12 - [c31]Joaquín Franco, Gregorio Bernabé, Juan Fernández, Manuel E. Acacio:
A Parallel Implementation of the 2D Wavelet Transform Using CUDA. PDP 2009: 111-118 - 2008
- [j8]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García:
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. 68(11): 1413-1424 (2008) - [j7]Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. J. Supercomput. 45(3): 341-364 (2008) - [j6]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distributed Syst. 19(8): 1044-1056 (2008) - [c30]Alberto Ros, Manuel E. Acacio, José M. García:
Scalable Directory Organization for Tiled CMP Architectures. CDES 2008: 112-118 - [c29]Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquín Franco:
Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. CSC 2008: 167-173 - [c28]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN 2008: 267-276 - [c27]J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC 2008: 541-554 - [c26]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC 2008: 555-568 - [c25]José L. Abellán, Juan Fernández, Manuel E. Acacio:
Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. ICCS (1) 2008: 456-465 - [c24]Antonio Flores, Manuel E. Acacio, Juan L. Aragón:
Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP 2008: 295-303 - [c23]Alberto Ros, Manuel E. Acacio, José M. García:
DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS 2008: 1-11 - [c22]J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco:
Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP 2008: 30-37 - [c21]José L. Abellán, Juan Fernández, Manuel E. Acacio:
CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. PDP 2008: 261-268 - 2007
- [j5]Gregorio Bernabé, Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José González:
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Comput. 33(1): 54-72 (2007) - [c20]Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) 2007: 752-757 - [c19]Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC 2007: 133-146 - [c18]Alberto Ros, Manuel E. Acacio, José M. García:
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC 2007: 147-160 - [c17]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA 2007: 157-168 - 2006
- [c16]Alberto Ros, Manuel E. Acacio, José M. García:
An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers 2006: 321-330 - [c15]Francisco J. Villa, Manuel E. Acacio, José M. García:
On the Evaluation of Dense Chip-Multiprocessor Architectures. ICSAMOS 2006: 21-27 - 2005
- [j4]Francisco J. Villa, Manuel E. Acacio, José M. García:
Evaluating IA-32 web servers through simics: a practical experience. J. Syst. Archit. 51(4): 251-264 (2005) - [j3]Manuel E. Acacio, José González, José M. García, José Duato:
A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. 16(1): 67-79 (2005) - [c14]Alberto Ros, Manuel E. Acacio, José M. García:
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par 2005: 582-591 - [c13]Francisco J. Villa, Manuel E. Acacio, José M. García:
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. HPCC 2005: 213-222 - [c12]Ricardo Fernández Pascual, José M. García, Gregorio Bernabé, Manuel E. Acacio:
Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. PDP 2005: 76-83 - 2004
- [j2]Manuel E. Acacio, José González, José M. García, José Duato:
An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Trans. Parallel Distributed Syst. 15(8): 755-768 (2004) - [c11]Francisco J. Villa, Manuel E. Acacio, José M. García:
On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. International Conference on Computational Science 2004: 541-544 - 2002
- [j1]Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel:
MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. Future Gener. Comput. Syst. 18(3): 317-333 (2002) - [c10]Manuel E. Acacio, José González, José M. García, José Duato:
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. IEEE PACT 2002: 155-164 - [c9]Manuel E. Acacio, José González, José M. García, José Duato:
A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. IPDPS 2002 - [c8]Manuel E. Acacio, José González, José M. García, José Duato:
Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. PDP 2002: 368-375 - [c7]Manuel E. Acacio, José González, José M. García, José Duato:
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. SC 2002: 1:1-1:12 - 2001
- [c6]Manuel E. Acacio, José González, José M. García, José Duato:
A New Scalable Directory Architecture for Large-Scale Multiprocessors. HPCA 2001: 97-106
1990 – 1999
- 1999
- [c5]Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel:
An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. ACPC 1999: 570-571 - [c4]Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte:
P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. IPPS/SPDP 1999: 563-568 - [c3]Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio:
The Parallel EM Algorithm and its Applications in Computer Vision. PDPTA 1999: 571-578 - [c2]Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel:
A Performance Evaluation of P-EDR in Different Parallel Environments. PDPTA 1999: 744-750 - [c1]Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte:
The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. PDPTA 1999: 1730-1736
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Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
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Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
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Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
.
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last updated on 2024-12-11 21:40 CET by the dblp team
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