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2020 – today
- 2024
[c20]Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. IMW 2024: 1-4- [c19]Hang-Ting Lue, Wei-Chen Chen, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F2 DRAM Below Equivalent 10nm Node. IMW 2024: 1-4 - [c18]Po-Hao Tseng, Shao-Yu Fang, Yu-Hsuan Lin, Feng-Ming Lee, Jhe-Yi Liao, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
3D-NAND based Filtering Cube with High Resolution 2D Query and Tunable Feature Length for Computational SSD. IMW 2024: 1-4 - [c17]Po-Hao Tseng, Yu-Hsuan Lin, Feng-Min Lee, Tian-Cig Bo, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Reliability Assessment for an In-3D-NAND Approximate Searching Solution. IRPS 2024: 1-6 - [c16]Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c15]Wei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu:
A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. IMW 2023: 1-4 - [c14]Po-Hao Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories. IMW 2023: 1-4 - [c13]Chih-Chang Hsieh, Hang-Ting Lue, Yung-Chun Li, Shuo-Nan Hung, Chun-Hsiung Hung, Keh-Chung Wang, Chih-Yuan Lu:
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c12]Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee, Chih-Chang Hsieh, Dai-Ying Lee, Keh-Chung Wang, Chih-Yuan Lu:
NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing. IMW 2022: 1-4 - [c11]Cheng-Lin Sung, Sheng-Ting Fan, Hang-Ting Lue, Wei-Chen Chen, Pei-Ying Du, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu:
First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures. IRPS 2022: 7 - [c10]Han-Wen Hu
, Wei-Chen Wang, Chung Kuang Chen, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Chao Lin, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Han-Sung Chen, Yuan-Hao Chang, Hsiang-Pang Li, Tei-Wei Kuo, Keh-Chung Wang, Meng-Fan Chang, Chun-Hsiung Hung, Chih-Yuan Lu:
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices. ISSCC 2022: 138-140 - [c9]Han-Wen Hu, Wei-Chen Wang, Yuan-Hao Chang, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Ming Huang, Chong-Ying Lee, Tzu-Hsiang Su, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Chung Kuang Chen, Han-Sung Chen, Hsiang-Pang Li, Tei-Wei Kuo, Meng-Fan Chang, Keh-Chung Wang, Chun-Hsiung Hung, Chih-Yuan Lu:
ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration. MICRO 2022: 763-783 - [c8]Po-Hao Tseng, Yu-Hsuan Lin, Feng-Ming Lee, Tian-Cig Bo, Yung-Chun Li, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories. VLSI Technology and Circuits 2022: 270-271 - 2021
- [c7]Hang-Ting Lue, Tzu-Hsuan Hsu, Cheng-Lin Sung, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu:
Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. IMW 2021: 1-4 - [c6]Cheng-Lin Sung, Hang-Ting Lue, Wei-Chen Chen, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu:
First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. IMW 2021: 1-4 - [c5]Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu:
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. IRPS 2021: 1-8 - [c4]Hang-Ting Lue, Han-Wen Hu, Tzu-Hsuan Hsu, Po-Kai Hsu, Keh-Chung Wang, Chih-Yuan Lu:
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. ISCAS 2021: 1-4 - 2020
- [c3]Chieh Roger Lo, Teng-Hao Yeh, Wei-Chen Chen, Hang-Ting Lue, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu:
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. IRPS 2020: 1-6 - [c2]Hang-Ting Lue, Po-Kai Hsu, Keh-Chung Wang, Chih-Yuan Lu:
Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper). IRPS 2020: 1-6
2010 – 2019
- 2014
- [j5]Li Sun, Quan Pan, Keh-Chung Wang, C. Patrick Yue:
A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2139-2149 (2014) - [c1]Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, Wing-Hung Ki, Keh-Chung Wang, C. Patrick Yue:
A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer. VLSIC 2014: 1-2
2000 – 2009
- 2000
- [j4]Andre G. Metzger, Charles E. Chang, Ken D. Pedrotti, Steve M. Beccue, Keh-Chung Wang, Peter M. Asbeck:
A 10-Gb/s high-isolation, 16×16 crosspoint switch implemented with AlGaAs/GaAs HBT's. IEEE J. Solid State Circuits 35(4): 593-600 (2000)
1990 – 1999
- 1996
- [j3]Ruai Yu, Steve M. Beccue, P. J. Zampardi, Richard L. Pierson, Anders Petersen, Keh-Chung Wang, John E. Bowers:
A packaged broad-band monolithic variable gain amplifier implemented in AlGaAs/GaAs HBT technology. IEEE J. Solid State Circuits 31(10): 1380-1387 (1996) - 1995
- [j2]Ken Poulton, Knud L. Knudsen, John J. Corcoran, Keh-Chung Wang, Randy B. Nubling, Richard L. Pierson, Mau-Chung Frank Chang, Peter M. Asbeck, R. T. Huang:
A 6-b, 4 GSa/s GaAs HBT ADC. IEEE J. Solid State Circuits 30(10): 1109-1118 (1995) - 1993
- [j1]Peter M. Asbeck, Mau-Chung Frank Chang, Keh-Chung Wang, Gerard J. Sullivan, Derek T. Cheung:
GaAs-based heterojunction bipolar transistors for very high performance electronic circuits. Proc. IEEE 81(12): 1709-1726 (1993)
Coauthor Index
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