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ORCIDMorihiro Kuga
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2020 – today
- 2024
[c31]Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS 2024: 1-6- 2023
- [j15]Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida:
An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 560-574 (2023) - 2022
- [c30]Morihiro Kuga, Masahiro Iida, Hideharu Amano:
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL 2022: 467 - 2021
- [c29]Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga:
Automation of Domain-specific FPGA-IP Generation and Test. HEART 2021: 4:1-4:6
2010 – 2019
- 2018
- [j14]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. 101-D(2): 335-343 (2018) - 2017
- [j13]Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. 100-D(4): 633-644 (2017) - [j12]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10: 63-70 (2017) - [c28]Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT 2017: 267-270 - [c27]Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART 2017: 18:1-18:6 - [c26]Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART 2017: 23:1-23:6 - 2016
- [j11]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44(4): 86-91 (2016) - [c25]Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE: An open-source platform for FPGA accelerators. FPT 2016: 205-208 - 2015
- [j10]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. 98-D(2): 252-261 (2015) - [j9]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10(3): 425-431 (2015) - [j8]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8: 116-122 (2015) - [c24]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Simple wafer stacking 3D-FPGA architecture. ICICDT 2015: 1-4 - [c23]Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC 2015: 110-115 - 2014
- [c22]Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL 2014: 1-6 - [c21]Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Zyndroid: An Android platform for software/hardware coprocessing. FPT 2014: 272-275 - [c20]Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Blokus Duo engine on a Zynq. FPT 2014: 374-377 - 2013
- [j7]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. 96-D(8): 1602-1612 (2013) - [j6]Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News 41(5): 71-76 (2013) - [c19]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA 2013: 271 - [c18]Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL 2013: 1-7 - [c17]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An automatic FPGA design and implementation framework. FPL 2013: 1-4 - [c16]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC 2013: 1-7 - [c15]Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC 2013: 192-197 - 2012
- [j5]Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2347-2356 (2012) - [c14]Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM 2012: 241 - [c13]Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault detection and avoidance of FPGA in various granularities. FPL 2012: 539-542 - [c12]Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT 2012: 220-223 - [c11]Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) 2012: 139-152 - [c10]Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) 2012: 392-404 - [c9]Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel physical defects recovery technique for FPGA-IP cores. ReConFig 2012: 1-7 - [c8]Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC 2012: 225-230 - 2011
- [j4]Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. 2(3): 35-48 (2011) - [j3]Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News 39(4): 82-85 (2011) - 2010
- [c7]Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM 2010: 47-54 - [c6]Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Power-aware FPGA routing fabrics and design tools. VLSI-SoC 2010: 67-72
2000 – 2009
- 2009
- [c5]Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
Memory Sharing Approach for TMR Softcore Processor. ARC 2009: 268-274 - [c4]Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
A novel states recovery technique for the TMR softcore processor. FPL 2009: 543-546 - 2004
- [c3]Hidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi:
EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. FPT 2004: 209-216 - 2002
- [j2]Toshinori Sueyoshi, Morihiro Kuga, Hidetomo Shibamura:
KITE microprocessor and CAE for computer science. Syst. Comput. Jpn. 33(8): 64-74 (2002)
1990 – 1999
- 1994
- [c2]Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori:
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN 1994: 427-434 - 1991
- [j1]Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita:
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. SIGARCH Comput. Archit. News 19(4): 14-29 (1991)
1980 – 1989
- 1989
- [c1]Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita:
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA 1989: 78-85
Coauthor Index
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last updated on 2024-08-27 22:58 CEST by the dblp team
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