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2020 – today
- 2020
[j8]Pao-Lung Chen
:
A Fully Synthesizable Ultra- ${N}$ Audio Frequency Multiplier for HDMI Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2134-2138 (2020)
2010 – 2019
- 2019
- [c10]Pao-Lung Chen:
An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering. ISPACS 2019: 1-2 - 2017
- [j7]Liming Xiu, Pao-Lung Chen:
A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed. IEEE Trans. Ind. Electron. 64(2): 1233-1240 (2017) - 2016
- [c9]Pao-Lung Chen:
A low-cost carry look-ahead adder for flying-adder frequency synthesizer. ICCE-TW 2016: 1-2 - [c8]Pao-Lung Chen:
An open-loop fractional divider based on direct phase synthesis. ICCE-TW 2016: 1-2 - 2015
- [j6]Pao-Lung Chen, Da-Chen Lee, Wei-Chia Li:
Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method. IEICE Trans. Electron. 98-C(6): 480-488 (2015) - [c7]Pao-Lung Chen:
Carry randomization with fractional control of a De Bruijn sequence. ICCE-TW 2015: 448-449 - [c6]Pao-Lung Chen, Ting-Yao Chen:
Digitally controlled oscillator with storage based randomization for spurs reduction. ICCE-TW 2015: 450-451 - 2013
- [c5]Pao-Lung Chen:
A jumping algorithm for calibration in multiphase delay locked loop. ICCA 2013: 1065-1069 - 2011
- [j5]Pao-Lung Chen, Chun-Chien Tsai:
An Interpolated Flying-Adder-Based Frequency Synthesizer. J. Electr. Comput. Eng. 2011: 871385:1-871385:11 (2011) - [c4]Pao-Lung Chen, Ke-Xin Lin:
Simulation-Based Analysis and Experimental Verification of Chaotic Circuits. FIRA 2011: 155-161 - 2010
- [j4]Pao-Lung Chen:
Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2616-2620 (2010) - [c3]Pao-Lung Chen, Tzu-Siang Wang, Jyun-Han Ciou:
A multiphase all-digital delay-locked loop with reuse SAR. APCCAS 2010: 943-946
2000 – 2009
- 2008
- [c2]Pao-Lung Chen:
Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop. ISCAS 2008: 2554-2557 - 2006
- [j3]Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee:
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE J. Solid State Circuits 41(6): 1275-1285 (2006) - 2005
- [j2]Pao-Lung Chen, Chen-Yi Lee:
A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3554-3563 (2005) - [j1]Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee:
A portable digitally controlled oscillator using novel varactors. IEEE Trans. Circuits Syst. II Express Briefs 52-II(5): 233-237 (2005) - [c1]Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee:
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) 2005: 4875-4878
Coauthor Index
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