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ORCIDTetsuya Matsumura
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2020 – today
- 2023
[c18]Yusei Horikawa, Renpei Yoshida, Seiji Mochizuki, Tetsuya Matsumura:
Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System. GCCE 2023: 817-818- [c17]Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura:
Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video. GCCE 2023: 852-853 - [c16]Yusei Horikawa, Seiji Mochizuki, Kousuke Imamura, Tetsuya Matsumura:
CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images. IoTaIS 2023: 169-174 - 2022
- [c15]Makoto Sugaya, Yusei Horikawa, Kazuma Mashiko, Tomoya Minagawa, Tetsuya Matsumura:
Implementation of Deep Learning-based Hierarchical Object Detection System for High-Resolution Images. GCCE 2022: 633-634
2010 – 2019
- 2019
- [j8]Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura:
Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1804-1812 (2019) - [c14]Kousuke Imamura, Satoshi Kanda, Saya Ohira, Yoshio Matsuda, Tetsuya Matsumura:
Scalable Architecture for High-Resolution Real-time Optical Flow Processor. IoTaIS 2019: 248-253 - [c13]Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki:
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. ISPACS 2019: 1-2 - 2018
- [c12]Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura:
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. IOTAIS 2018: 155-161 - [c11]Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura:
Automatic Design Environment using High-level Synthesis for Reconfigurable 3D Sound Processor. ISPACS 2018: 325-330 - 2017
- [j7]Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda:
A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(10): 2123-2134 (2017) - [j6]Yu Suzuki, Masato Ito, Satoshi Kanda, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura:
Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2888-2900 (2017) - [c10]Saya Ohira, Tetsuya Matsumura:
Design for three-dimensional sound processor using high-level synthesis. DDECS 2017: 190-193 - 2016
- [j5]Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto:
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(5): 917-928 (2016) - [c9]Tetsuya Matsumura, Kousuke Imamura, Yoshifumi Kawamura, Yoshio Matsuda:
Automatic rule registration and deletion function on a packet lookup engine LSI. ISPACS 2016: 1-6 - 2015
- [j4]Ippei Nishitani, Tetsuya Matsumura, Mayumi Ozawa, Ayanori Yorozu
, Masaki Takahashi:
Human-centered X-Y-T-space path planning for mobile robot in dynamic environments. Robotics Auton. Syst. 66: 18-26 (2015) - [c8]Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda:
A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm. DDECS 2015: 31-36 - 2014
- [j3]Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa:
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 575-584 (2014) - [c7]Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda:
The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS 2014: 183-188 - 2013
- [c6]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda:
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED 2013: 438-441 - 2012
- [c5]Ayanori Yorozu, Takafumi Suzuki, Tetsuya Matsumura, Masaki Takahashi:
Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot Considering Shape of the Robot and Movable Area by Heights. IAS (1) 2012: 91-100 - [c4]Ayanori Yorozu, Takafumi Suzuki, Tetsuya Matsumura, Masaki Takahashi:
Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot - 2nd Report: Robot Model Considering Moving Parts and Evaluation of Movable Area by Heights. ICINCO (2) 2012: 451-454 - 2011
- [c3]Masaki Takahashi, Takafumi Suzuki, Tetsuya Matsumura, Ayanori Yorozu:
Obstacle Avoidance with Simultaneous Translational and Rotational Motion Control for Autonomous Mobile Robot. ICINCO (2) 2011: 5-13
2000 – 2009
- 2002
- [j2]Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuya Matsumura:
A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. IEEE J. Solid State Circuits 37(3): 450-454 (2002)
1990 – 1999
- 1999
- [c2]Satoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida:
A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. CICC 1999: 95-98 - 1998
- [c1]Atsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi:
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. CICC 1998: 169-172 - 1990
- [j1]Shin-ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shuichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba:
A 24-b 50-ns digital image signal processor. IEEE J. Solid State Circuits 25(6): 1484-1493 (1990)
Coauthor Index
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