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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 9
Volume 9, Number 1, February 2001
- Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Arne Schulz, Enrico Macii, Wolfgang Nebel:
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs. 3-14 - Tajana Simunic, Luca Benini, Giovanni De Micheli:
Energy-efficient design of battery-powered embedded systems. 15-28 - Thomas L. Martin, Daniel P. Siewiorek
:
Nonideal battery and main memory effects on CPU speed-setting for low power. 29-34 - Oliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S.-K. Cheng:
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. 34-41 - Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara:
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. 42-51 - Suhwan Kim, Marios C. Papaefthymiou:
True single-phase adiabatic circuitry. 52-63 - Scott E. Meninger, José Oscar Mur-Miranda, Rajeevan Amirtharajah, Anantha P. Chandrakasan, Jeffrey H. Lang:
Vibration-to-electric energy conversion. 64-76 - Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
Reducing leakage in a high-performance deep-submicron instruction cache. 77-89 - Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Robust subthreshold logic for ultra-low power operation. 90-99 - Francesco Svelto, Stefano Deantoni, Giampiero Montagna, Rinaldo Castello:
Implementation of a CMOS LNA plus mixer for GPS applications with no external components. 100-104 - Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin:
Design considerations for databus charge recovery. 104-106 - Ranga Vemuri, Rajesh K. Gupta:
Guest editorial reconfigurable and adaptive VLSI systems. 107-108 - Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada, Akira Nagoya:
Solving satisfiability problems using reconfigurable computing. 109-116 - Fatih Kocan, Daniel G. Saab:
ATPG for combinational circuits on configurable hardware. 117-129 - Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm:
An automated process for compiling dataflow graphs into reconfigurable hardware. 130-139 - V. Srinivasan, Sriram Govindarajan, Ranga Vemuri:
Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. 140-158 - Miron Abramovici, Charles E. Stroud:
BIST-based test and diagnosis of FPGA logic blocks. 159-172 - Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh:
A formal approach to context scheduling for multicontext reconfigurable architectures. 173-185 - Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai:
Design and analysis of a dynamically reconfigurable three-dimensional FPGA. 186-196 - Philip Heng Wai Leong, Chiu-Wing Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong:
A bitstream reconfigurable FPGA implementation of the WSAT algorithm. 197-201 - Brad L. Hutchings, Brent E. Nelson:
Unifying simulation and execution in a design environment for FPGA systems. 201-205 - Oskar Mencer, Marco Platzner, Martin Morf, Michael J. Flynn:
Object-oriented domain specific compilers for programming FPGAs. 205-210 - E. Cantó, Juan Manuel Moreno, Joan Cabestany, Ignacio Lacadena, Josep Maria Insenser:
A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs. 210-218 - Andrew A. Duncan, David C. Hendry, Peter Gray:
The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines. 218-223 - Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Structural analysis and generation of synthetic digital circuits with memory. 223-226 - Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Raoul Tawel, Taher Daud, Anil Thakoor:
Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips. 227-232
Volume 9, Number 2, April 2001
- Michael Gschwind, Valentina Salapura, Dietmar Maurer:
FPGA prototyping of a RISC processor core for embedded applications. 241-250 - Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping. 251-260 - Rong Lin:
Reconfigurable parallel inner product processor architectures. 261-272 - Jörg Henkel, Rolf Ernst:
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques. 273-289 - Irith Pomeranz, Sudhakar M. Reddy:
A built-in self-test method for diagnosis of synchronous sequential circuits. 290-296 - Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
A hardware cost minimized fast Phong shader. 297-304 - Curt Schurgers, Francky Catthoor, Marc Engels:
Memory optimization of MAP turbo decoder algorithms. 305-312 - Santanu Dutta:
Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor. 313-328 - Yi-Min Jiang, Kwang-Ting Cheng:
Vector generation for power supply noise estimation and verification of deep submicron designs. 329-340 - Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh:
Fast floorplanning for effective prediction and construction. 341-351 - Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta:
A physical design tool for built-in self-repairable RAMs. 352-364 - Mauro Olivieri:
Design of synchronous and asynchronous variable-latency pipelined multipliers. 365-376 - Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi:
Partial bus-invert coding for power optimization of application-specific systems. 377-383 - Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. 383-389 - P. Pant, R. K. Roy, A. Chatterjee:
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits. 390-394 - Mircea R. Stan:
Low-power CMOS with subvolt supply voltages. 394-400 - Joseph N. Kozhaya, Farid N. Najm:
Power estimation for large sequential circuits. 400-407 - Abdel Ejnioui, N. Ranganathan:
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. 407-410
Volume 9, Number 3, June 2001
- Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Stream synthesis for efficient power simulation based on spectral transforms. 417-426 - Wanli Jiang, Bapiraju Vinnakota:
Defect-oriented test scheduling. 427-438 - Marco Cavadini, Matthias Wosnitza, Gerhard Tröster:
Multiprocessor system for high-resolution image correlation in real time. 439-449 - Woojin Jin, Yungseon Eo, William R. Eisenstadt, Jongin Shim:
Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects. 450-460 - Tomás Bautista, Antonio Núñez:
Quantitative study of the impact of design and synthesis options on processor core performance. 461-473 - Johnson Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak:
Exploring the diversity of multimedia systems. 474-485
Volume 9, Number 4, August 2001
- Shih-Arn Hwang, Cheng-Wen Wu:
Unified VLSI systolic array design for LZ data compression. 489-499 - Tony Givargis, Frank Vahid, Jörg Henkel:
Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs. 500-508 - Huesung Kim, Arun K. Somani, Akhilesh Tyagi:
A reconfigurable multifunction computing cache architecture. 509-523 - Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
FunState-an internal design representation for codesign. 524-544 - Adam J. Elbirt, W. Yip, B. Chetwynd, Christof Paar:
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists. 545-557 - Mauro Olivieri:
Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers". 558-559
Volume 9, Number 5, October 2001
- King-Chu Hung, Yao-Shan Hung, Yu-Jung Huang:
A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform. 565-576 - Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji:
Technology mapping for high-performance static CMOS and pass transistor logic designs. 577-589 - Muhammad M. Khellah, Mohamed I. Elmasry:
A low-power high-performance current-mode multiport SRAM. 590-598 - Elie Torbey, John P. Knight:
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms. 599-607 - Massimo Alioto, Gaetano Palumbo:
Power estimation in adiabatic circuits: a simple and accurate model. 608-615 - Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh:
On gate level power optimization using dual-supply voltages. 616-629 - Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Discrete-time battery models for system-level low-power design. 630-640 - Dilip V. Sarwate, Naresh R. Shanbhag:
High-speed architectures for Reed-Solomon decoders. 641-655 - Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang:
Narrow bus encoding for low-power DSP systems. 656-660 - HyungWon Kim, John P. Hayes:
Delay fault testing of IP-based designs via symbolic path modeling. 661-678 - Irith Pomeranz, Sudhakar M. Reddy:
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. 679-689 - Per Bjuréus, Axel Jantsch:
Modeling of mixed control and dataflow systems in MASCOT. 690-703 - Xiaohong Jiang, Susumu Horiguchi:
Statistical skew modeling for general clock distribution networks in presence of process variations. 704-717 - Zhanping Chen, Liqiong Wei, Kaushik Roy:
On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. 718-725 - Chang-Ki Kwon, Kwyro Lee:
Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques. 726-729 - Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang:
An on-chip march pattern generator for testing embedded memory cores. 730-735
Volume 9, Number 6, December 2001
- Asim Smailagic:
Guest editorial: system level design. 741-742 - Luc Séméria, Koichi Sato, Giovanni De Micheli:
Synthesis of hardware models in C with pointers and complex data structures. 743-756 - Manish Bhardwaj, Rex Min, Anantha P. Chandrakasan:
Quantifying and enhancing power awareness of VLSI systems. 757-772 - Fabian Wolf, Rolf Ernst, Wei Ye:
Path clustering in software timing analysis. 773-782 - James Smith, Giovanni De Micheli:
Polynomial circuit models for component matching in high-level synthesis. 783-800 - Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye:
Influence of compiler optimizations on system power. 801-804 - Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas:
Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. 805-812 - Rajamohana Hegde, Naresh R. Shanbhag:
Soft digital signal processing. 813-823 - Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression-based register-transfer level testability analysis and optimization. 824-832 - Xiaobo Sharon Hu, Tao Zhou, Edwin Hsing-Mean Sha:
Estimating probabilistic timing performance for real-time embedded systems. 833-844 - Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty:
Automatic generation and compaction of March tests for memory arrays. 845-857 - Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh:
A framework for reconfigurable computing: task scheduling and context management. 858-873 - Huapeng Wu, M. Anwar Hasan:
Efficient exponentiation using weakly dual basis. 874-879 - Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino:
Parameterized RTL power models for soft macros. 880-887 - David M. Harris, Sam Naffziger:
Statistical clock skew modeling with data delay variations. 888-898 - Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). 899-912 - Phillip Christie:
A differential equation for placement analysis. 913-921 - James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Impact of three-dimensional architectures on interconnects in gigascale integration. 922-928 - Jason Cong, Tianming Kong, Z. D. Pan:
Buffer block planning for interconnect planning and prediction. 929-937 - Peter Verplaetse, Dirk Stroobandt, Jan M. Van Campenhout:
A stochastic model for the interconnection topology of digital circuits. 938-942 - Srinivas Bodapati, Farid N. Najm:
Prelayout estimation of individual wire lengths. 943-958 - Javier D. Bruguera, Tomás Lang:
Multilevel reverse most-significant carry computation. 959-962 - Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Exploiting the on-chip inductance in high-speed clock distribution networks. 963-973 - Marcello Lajolo:
Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. 974-982 - Chingwei Yeh, Yin-Shuin Kang:
Cell-based layout techniques supporting gate-level voltage scaling for low power. 983-986
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