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ORCIDMicroprocessors and Microsystems, Volume 29
Volume 29, Number 1, February 2005
- M. Thaduri, Seong-Moo Yoo, Rhonda Kay Gaede:
An efficient VLSI implementation of IDEA encryption algorithm using VHDL. 1-7 - Yichuan Jiang, Zhengyou Xia
, Yiping Zhong, Shiyong Zhang:
An adaptive adjusting mechanism for agent distributed blackboard architecture. 9-20 - S. B. Wang, S. B. Zhou, G. Huang, B. F. Xiong, S. H. Chen, X. J. Yi:
Fabrication of 128×128 element optical switch array by micromachining technology. 21-25 - Bruce R. Childers, Jack W. Davidson:
An infrastructure for designing custom embedded wide counterflow pipelines. 27-40 - Kil-Whan Lee, Woo-Chan Park, Il-San Kim, Tack-Don Han:
A pixel cache architecture with selective placement scheme based on z-test result. 41-46
Volume 29, Numbers 2-3, April 2005
- Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
Advances in FPGA tools and techniques. 47-49 - Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler:
Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. 51-62 - Rolf Enzler, Christian Plessl, Marco Platzner:
System-level performance evaluation of reconfigurable processors. 63-73 - M. A. Aguirre, Jonathan Noel Tombs, Vicente Baena Lecuyer, Jose Luis Mora, Juan Manuel Carrasco Solís, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo:
Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems. 75-85 - John A. Nestor:
L3: An FPGA-based multilayer maze routing accelerator. 87-97 - L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti:
Pseudo-online testing methodologies for various components of field programmable gate arrays. 99-119 - Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Peter F. Curran, Kuan Zhou, Bryan S. Goda, John F. McDonald:
A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. 121-131
Volume 29, Number 4, May 2005
- K. N. Vikram, Vinita Vasudevan:
Hardware-software co-simulation of bus-based reconfigurable systems. 133-144 - Tony Givargis, David Eppstein:
Memory reference caching for activity reduction on address buses. 145-153 - Kaisa Haapala, Ville Lappalainen, Timo Hämäläinen:
Experimental parallel implementation of a wavelet-based still image encoder. 155-167 - Xiaofan Yang, Graham M. Megson, David J. Evans:
A comparison-based diagnosis algorithm tailored for crossed cube multiprocessor systems. 169-175 - Jong-Yeol Lee, Seong Ik Cho, In-Cheol Park:
Performance enhancement of embedded software based on new register allocation technique. 177-187
Volume 29, Number 5, June 2005
- Marcos R. Frankowiak, Roger I. Grosvenor, Paul W. Prickett:
A Petri-net based distributed monitoring system using PIC microcontrollers. 189-196 - W. L. Yeung, S. A. Schneider:
Formal verification of fault-tolerant software design: the CSP approach. 197-209 - Andres Upegui, Carlos Andrés Peña-Reyes, Eduardo Sanchez:
An FPGA platform for on-line topology exploration of spiking neural networks. 211-223 - Nathan T. Slingerland, Alan Jay Smith:
Multimedia extensions for general purpose microprocessors: a survey. 225-246
Volume 29, Number 6, August 2005
- Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris:
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. 247-259 - Chunlin Li, Layuan Li:
A distributed decomposition policy for computational grid resource allocation optimization based on utility functions. 261-272 - Kai-Feng Wang, Zhenzhou Ji, Mingzeng Hu:
Path-based next N trace prefetch in trace processors. 273-288 - Yichuan Jiang, Zhengyou Xia, Shiyong Zhang:
A novel defense model for dynamic topology network based on mobile agent. 289-297 - Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo:
Microprocessor-based FPGA implementation of SPIHT image compression subsystems. 299-305
Volume 29, Number 7, September 2005
- Bonifacio Martín-del-Brío, Antonio Bono-Nuez, Nicolás J. Medrano-Marqués:
Self-organizing maps for embedded processor selection. 307-315 - Seong-Moo Yoo, Deen Kotturi, W. David Pan, John Blizzard:
An AES crypto chip using a high-speed parallel pipelined architecture. 317-326 - W. Kurdthongmee:
Design and implementation of an FPGA-based multiple-colour LED display board. 327-336 - Behnam Robatmili, Nasser Yazdani, Mehrdad Nourani:
Optimizing SMT processors for IP-packet processing. 337-349 - Ayan Banerjee, Anindya Sundar Dhar:
Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation. 351-357
Volume 29, Numbers 8-9, November 2005
- Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
Recent advances in computer vision and image processing using reconfigurable hardware. 359-362 - Manjunath Gangadhar, Dinesh Bhatia:
FPGA based EBCOT architecture for JPEG 2000. 363-373 - Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado, Armando Astarloa:
Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications. 375-380 - Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor. 381-391 - Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses:
The rapid prototyping experience of an H.263 video coder onto FPGA. 393-404 - N. Sudha:
A pipelined array architecture for Euclidean distance transformation and its FPGA implementation. 405-410 - Ana Toledo Moreo, Pedro Javier Navarro Lorente, F. Soto Valles, Juan Suardíaz Muro, Carlos Fernández Andrés:
Experiences on developing computer vision hardware algorithms using Xilinx system generator. 411-419
Volume 29, Number 10, December 2005
- Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias:
Multiprocessor SoPC-Core for FAT volume computation. 421-434 - Gareth Lee, George J. Milne:
Programming paradigms for reconfigurable computing. 435-450 - Byung-Soo Choi:
Cost effective mixed-type value predictor using distributed classification method. 451-462
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