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ORCIDVLSI-SoC 2020: Salt Lake City, UT, USA - Selected Papers
- Andrea Calimera
, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis:
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 621, Springer 2021, ISBN 978-3-030-81640-7 - David Cordova, Wim Cops, Yann Deval, François Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin:
Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI. 1-19 - Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli:
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. 21-37 - Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein:
Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring. 39-63 - Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff:
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. 65-85 - Alessandro Veronesi, Davide Bertozzi, Milos Krstic:
Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform. 87-112 - Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek:
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. 113-131 - Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens:
Learning Based Timing Closure on Relative Timed Design. 133-148 - Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury:
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. 149-178 - Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli:
From Informal Specifications to an ABV Framework for Industrial Firmware Verification. 179-204 - Josie Esteban Rodriguez Condia, Matteo Sonza Reorda:
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs. 205-233 - Jonas Gava, Ricardo Reis, Luciano Ost:
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique. 235-253 - Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo:
SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption. 255-278 - Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. 279-300 - Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand, Abhishek Kumar:
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. 301-321 - Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury:
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. 323-341 - Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. 343-361
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