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ORCIDVLSI-SoC 2014: Playa del Carmen, Mexico
- Lorena Garcia:
22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014. IEEE 2014, ISBN 978-1-4799-6016-3 - Vladan Popovic, Yusuf Leblebici:
Reconfigurable forward homography estimation system for real-time applications. 1-6 - Shilpa Pendyala, Srinivas Katkoori
:
Self similarity and interval arithmetic based leakage optimization in RTL datapaths. 1-6 - Matthias Jung, Christian Weis, Norbert Wehn, MohammadSadegh Sadri, Luca Benini:
Optimized active and power-down mode refresh control in 3D-DRAMs. 1-6 - Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian:
Realizing a security aware triple modular redundancy scheme for robust integrated circuits. 1-6 - Laurent Chusseau, Rachid Omarouayache, Jérémy Raoult, Sylvie Jarrix, Philippe Maurine, Karim Tobich, Alexandre Boyer, Bertrand Vrignon, John Shepherd, Thanh-Ha Le, Maël Berthier, Lionel Rivière, Bruno Robisson, Anne-Lise Ribotta:
Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI). 1-6 - Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri:
AES design space exploration new line for scan attack resiliency. 1-6 - Hiroyuki Yamauchi, Worawit Somha:
Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation. 1-6 - K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle:
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. 1-6 - Alfonso Martínez-Cruz, Ricardo Barrón Fernández, Herón Molina-Lozano:
Automated functional coverage directed for complex digital systems. 155-156 - Masahiro Fujita, Alan Mishchenko:
Logic synthesis and verification on fixed topology. 1-6 - Masaki Nakanishi, Miki Matsuyama, Yumi Yokoo:
A quantum algorithm processor architecture based on register reordering. 1-6 - Javier Osorio Figueroa, Mónico Linares Aranda:
Study of on-chip vias of resonant rotary traveling wave oscillators. 157-158 - Wei-Yu Tsai, Huichu Liu, Xueqing Li, Vijaykrishnan Narayanan:
Low-power high-speed current mode logic using Tunnel-FETs. 1-6 - Jeffrey McDaniel, Brendon Parker, Philip Brisk:
Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips. 1-6 - Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
Towards energy effective LDPC decoding by exploiting channel noise variability. 1-6 - Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier:
Laser-induced fault effects in security-dedicated circuits. 1-6 - Gabriele Miorandi, Alberto Ghiribaldi, Steven M. Nowick, Davide Bertozzi:
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study. 1-6 - Alberto Nannarelli:
Decimal engine for energy-efficient multicore processors. 1-6 - Zoltán Endre Rákossy:
Modeling, analysis and exploration of layers: A 3D computing architecture. 159-160 - Filippo Cucchetto, Alessandro Lonardi, Graziano Pravadelli:
A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms. 1-6 - Ruping Cao, John Ferguson, Fabien Gays, Youssef Drissi, Alexandre Arriordaz, Ian O'Connor:
Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification. 1-6 - Giovanni Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Alessandro Paccagnella:
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. 1-6 - Matheus T. Moreira, Ney Laert Vilar Calazans:
Advances on the state of the art in QDI design. 163-164 - Sreenivaas S. Muthyala, Nur A. Touba:
Reducing test time for 3D-ICs by improved utilization of test elevators. 1-6 - Sidinei Ghissoni, Eduardo A. C. da Costa, Angelo Goncalves da Luz:
Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors. 1-6 - Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart:
Electromagnetic analysis and fault injection onto secure circuits. 1-6 - Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip. 1-6 - Zhen Li, Sébastien Le Beux, Ian O'Connor, Christelle Monat, Xavier Letartre:
Complementary logic interface for high performan optical computing with OLUT. 1-6 - Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán:
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. 1-6 - Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto:
A low power 720p motion estimation processor with 3D stacked memory. 1-6 - Jesus-Andres Mendoza-Bonilla, Alejandro Cortez-Ibarra, Edgar-Andrei Vega-Ochoa, Francisco Rangel-Patino, Brandon Gore:
Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation. 1-6 - Farshad Moradi, Jens Kargaard Madsen:
Improved read and write margins using a novel 8T-SRAM cell. 1-5 - Moon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim:
Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. 1-6 - Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay:
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. 1-6 - Liang Wang, Xiaohang Wang, Terrence S. T. Mak:
Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip. 1-6 - Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione:
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. 1-6 - Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Mark Zwolinski:
A novel non-minimal turn model for highly adaptive routing in 2D NoCs. 1-6 - Jeffrey McDaniel, Daniel T. Grissom, Philip Brisk:
Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion. 1-6 - Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
Soft error effects analysis and mitigation in VLIW safety-critical applications. 1-6 - Dongwoo Lee, Kiyoung Choi:
Energy-efficient partitioning of hybrid caches in multi-core architecture. 1-6 - Bernard van Gastel, Freek Verbeek, Julien Schmaltz:
Inference of channel types in micro-architectural models of on-chip communication networks. 1-6 - Andrew A. Kennings, Nima Karimpour Darav, Laleh Behjat:
Detailed placement accounting for technology constraints. 1-6 - Hari Anand Ravi, Mayank Goel, Prasad Bhilawadi:
Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers. 1-5 - Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers. 1-6
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