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ORCIDICSAMOS 2012: Samos, Greece
- 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012. IEEE 2012, ISBN 978-1-4673-2295-9
- John McAllister, Shuvra S. Bhattacharyya
:
Preface. - John Goodacre:
The homogeneity of architecture in a heterogeneous world. - Edward A. Lee:
It's about time. - Oskar Mencer:
Maximum performance computing for exascale applications. - Dominik Auras, Andreas Minwegen, Uwe Deidersen:
Just-in-Time Verification in ADL-based processor design. 1-6 - Roberta Piscitelli, Andy D. Pimentel:
Interleaving methods for hybrid system-level MPSoC design space exploration. 7-14 - Angeliki Kritikakou, Francky Catthoor, George Athanasiou, Vasilios I. Kelefouras, Costas E. Goutis:
A template-based methodology for efficient microprocessor and FPGA accelerator co-design. 15-22 - Michael Andersch, Chi Ching Chi, Ben H. H. Juurlink:
Using OpenMP superscalar for parallelization of embedded and consumer applications. 23-32 - Rainer Kiesel, Martin Streubühr, Christian Haubelt, Anestis Terzis, Jürgen Teich:
Virtual prototyping for efficient multi-core ECU development of driver assistance systems. 33-40 - Amine Anane, El Mostapha Aboulhamid, Yvon Savaria:
System modeling and multicore simulation using transactions. 41-50 - Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny:
HNOCS: Modular open-source simulator for Heterogeneous NoCs. 51-57 - Ricardo A. Velásquez, Pierre Michaud, André Seznec:
BADCO: Behavioral Application-Dependent Superscalar Core model. 58-67 - Siegfried Brandstätter, Mario Huemer:
An application-specific Network-on-Chip for control architectures in RF transceivers. 68-75 - Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras:
A framework for efficient cache resizing. 76-85 - Alessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich:
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. 86-95 - Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Nasser Yazdani:
A tightly-coupled multi-core cluster with shared-memory HW accelerators. 96-103 - Robert M. Seepers, Christos Strydis, Georgi Nedeltchev Gaydadjiev:
Architecture-level fault-tolerance for biomedical implants. 104-112 - Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silvén:
Reconfigurable miniature sensor nodes for condition monitoring. 113-119 - Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Counting stream registers: An efficient and effective snoop filter architecture. 120-127 - Rosilde Corvino, Abdoulaye Gamatié, Marc Geilen, Lech Józwiak:
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops. 128-135 - Matthew Milford, John McAllister:
Automatic FPGA synthesis of memory intensive C-based kernels. 136-143 - Anastasia Stulova, Rainer Leupers, Gerd Ascheid:
Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs. 144-151 - Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin:
K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph. 152-159 - Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi:
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph. 160-167 - Daniel Baudisch, Jens Brandt, Klaus Schneider:
Out-Of-order execution of synchronous data-flow networks. 168-175 - Jochem H. Rutgers, Marco Jan Gerrit Bekooij, Gerard J. M. Smit:
An efficient asymmetric distributed lock for embedded multiprocessor systems. 176-182 - Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig:
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. 183-192 - Frederico Pratas, Pedro Tomás, Pedro Trancoso, Leonel Sousa:
Energy efficient stream-based configurable architecture for embedded platforms. 193-200 - Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio:
TaBit: A framework for task graph to bitstream generation. 201-208 - Lauri Matilainen, Lasse Lehtonen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen:
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata. 209-216 - Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen:
Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology. 217-226 - Diana Göhringer, Pedro C. Diniz:
Special session on "programming paradigms for reconfigurable multi-core embedded systems". 227 - Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire:
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. 228-235 - Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg:
Adaptive reinforcement learning method for networks-on-chip. 236-243 - Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker:
Adaptive processor architecture - invited paper. 244-251 - Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris:
Adaptive dynamic memory allocators by estimating application workloads. 252-259 - João M. P. Cardoso, Tiago Carvalho, João Teixeira, Pedro C. Diniz, Fernando M. Gonçalves, Zlatko Petrov:
Hardware/software specialization through aspects: The LARA approach. 260-267 - George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Ménard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas:
From Scilab to multicore embedded systems: Algorithms and methodologies. 268-275 - Holger Blume:
Special session on "FPGA-based emulation of hardware architectures". 276 - Joseph Rothman, Chen Chang:
BEE technology overview. 277 - Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. 278-285 - Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras:
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. 286-293 - Matthias Korb, Tobias G. Noll:
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations. 294-301 - David May, Walter Stechele:
An FPGA-based probability-aware fault simulator. 302-309 - Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel:
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. 310-317 - Ed F. Deprettere:
Special session on "aspects of Cyber-Physical Systems". 318 - Joseph Sifakis:
Rigorous design of cyber-physical systems. 319 - Marc Geilen, Sander Stuijk, Twan Basten:
Predictable dynamic embedded data processing. 320-327 - Peter Marwedel, Michael Engel:
Efficient computing in cyber-physical systems. 328-332 - Martin Schoeberl:
Is time predictability quantifiable? 333-338 - Jan F. Broenink, Yunyun Ni:
Model-driven robot-software design using integrated models and co-simulation. 339-344 - Andreas Herkersdorf:
Multicore enablement for Cyber Physical Systems. 345 - Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy:
Challenges in automotive cyber-physical systems design. 346-354 - Michael Glaß, Jürgen Teich, Liyuan Zhang:
A co-simulation approach for system-level analysis of embedded control systems. 355-362 - Shuvra S. Bhattacharyya:
Instrumentation techniques for cyber-physical systems using the targeted dataflow interchange format. 363 - Patrice Quinton, Anne-Marie Chana, Steven Derrien:
Efficient hardware implementation of data-flow parallel embedded systems. 364-371
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