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ORCID13. FPGA 2005: Monterey, CA, USA
- Herman Schmit, Steven J. E. Wilton:
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005. ACM 2005, ISBN 1-59593-029-9
New FPGA architectures
- Andy Gean Ye, Jonathan Rose:
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. 3-13 - David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose:
The Stratix II logic and routing architecture. 14-20 - Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh:
HARP: hard-wired routing pattern FPGAs. 21-29
Advances in FPGA CAD
- Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Skew-programmable clock design for FPGA and skew-aware placement. 33-40 - Yuzheng Ding, Peter Suaris, Nan-Chi Chou:
The effect of post-layout pin permutation on timing. 41-50 - Gang Chen, Jason Cong:
Simultaneous timing-driven placement and duplication. 51-59
Computation algorithms for FPGA
- Ling Zhuo, Viktor K. Prasanna:
Sparse Matrix-Vector multiplication on FPGAs. 63-74 - Michael DeLorimier, André DeHon:
Floating-point sparse matrix-vector multiply for FPGAs. 75-85 - Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev
:
64-bit floating-point FPGA matrix multiplication. 86-95
Computation techniques for FPGAs
- Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors. 99-106 - Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster:
An FPGA-based VLIW processor with custom hardware execution. 107-117 - Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid:
Techniques for synthesizing binaries to an advanced register/memory structure. 118-124
New directions for programmable devices
- André DeHon:
Design of programmable interconnect for sublithographic programmable logic arrays. 127-137 - Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. 138-148 - Ghazanfar Asadi, Mehdi Baradaran Tahoori:
Soft error rate estimation and mitigation for SRAM-based FPGAs. 149-160
Synthesis and timing analysis for FPGAs
- Song Peng, David Fang, John Teifel, Rajit Manohar:
Automated synthesis for asynchronous FPGAs. 163-173 - Mike Hutton, David Karchmer, Bryan Archell, Jason Govig:
Efficient static timing analysis and applications using edge masks. 174-183 - Heidi E. Ziegler, Mary W. Hall:
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs. 184-195
FPGA circuit design and layout
- Yan Lin, Fei Li, Lei He:
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. 199-207 - Andrea Lodi, Luca Ciccarelli, Roberto Giansante:
Combining low-leakage techniques for FPGA routing design. 208-214 - Ian Kuon, Aaron Egier, Jonathan Rose:
Design, layout and verification of an FPGA using automated tools. 215-226
Novel FPGA applications
- Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell:
Hyper customized processors for bio-sequence database scanning on FPGAs. 229-237 - Haoyu Song, John W. Lockwood:
Efficient packet classification for network intrusion detection using FPGA. 238-245 - Graham Schelle, Dirk Grunwald:
CUSP: a modular framework for high speed network applications on FPGAs. 246-257
Posters: New CAD techniques and methods
- Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl:
Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only). 262 - Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel, Carlos A. Valderrama, Abel Guilhermino Silva-Filho, Paulo Sérgio B. do Nascimento:
A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only). 262 - Yirong OuYang, Jiarong Tong:
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only). 263 - Leos Kafka, Rafal Kielbik, Rudolf Matousek, Juan Manuel Moreno:
VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only). 263 - Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
3D FPGAs: placement, routing, and architecture evaluation (abstract only). 263 - Deepak Rautela, Rajendra S. Katti:
Efficient utilization of heterogeneous routing resources for FPGAs (abstract only). 264 - Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel:
Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). 264 - Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano:
Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. 265 - E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan:
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). 265 - Akshay Sharma, Carl Ebeling, Scott Hauck:
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). 266 - Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh:
Routing algorithms: enhancing routability & enabling ECO (abstract only). 266 - Wenyin Fu, Katherine Compton:
An execution environment for reconfigurable computing (abstract only). 267 - Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). 267
Posters: FPGA architectures and circuits
- Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume:
Energy-efficient FPGA interconnect architecture design (abstract only). 268 - Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Exploration of heterogeneous reconfigurable architectures (abstract only). 268 - Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). 269 - Wen Yujie, Jiarong Tong, Charles C. Chiang:
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only). 269 - Chul Kim, A. M. Rassau, Mike Myung-Ok Lee:
3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only). 270 - Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon:
Dynamic hardware multiplexing for coarse grain reconfigurable architectures. 270 - Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer:
Soft multiprocessor systems for network applications (abstract only). 271 - Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers:
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). 271 - Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das:
Hierarchical LUT structures for leakage power reduction (abstract only). 272 - Akhilesh Kumar, Mohab Anis:
Dual-Vt FPGA design for leakage power reduction (abstract only). 272 - Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee:
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). 273
Posters: Novel applications of reconfigurability
- Roman Bartosinski, Martin Danek, Petr Honzík, Rudolf Matousek:
Dynamic reconfiguration in FPGA-based SoC designs (abstract only). 274 - Jacqueline E. Rice, Kenneth B. Kent, Troy Ronda, Zhao Yong:
Configurable hardware solutions for computing autocorrelation coefficients: a case study (abstract only). 274 - Yong-Gang Wang, Tian-Xin Yan:
Design and implementation of packet classification with FPGA (abstract only). 275 - Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho:
A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only). 275 - Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj:
Image processing library for reconfigurable computers (abstract only). 276 - Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin:
A 2005 review of FPGA arithmetic (abstract only). 276 - Edward Brown, James Irvine, Bill Wilkie:
Rapid prototyping of a test harness for forward error correcting codes (abstract only). 276 - Michael Attig, John W. Lockwood:
A framework for rule processing in reconfigurable network systems (abstract only). 277 - Sven Heithecker, Rolf Ernst:
An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only). 277 - Khaled Benkrid, Samir Belkacemi:
An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only). 278 - Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha:
Reconfigurable computers: an empirical analysis (abstract only). 278 - Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte:
A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only). 278 - Jianchun Li, Christos A. Papachristou, Raj Shekhar:
Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only). 279 - Bryan Catanzaro, Brent E. Nelson:
Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). 279 - Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi:
An FPGA generator for multipoint distributed random variables (abstract only). 280 - Bo Yang, Nikhil Joshi, Ramesh Karri:
A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). 280
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