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ORCID49th DAC 2012: San Francisco, CA, USA
- Patrick Groeneveld, Donatella Sciuto, Soha Hassoun:
The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012. ACM 2012, ISBN 978-1-4503-1199-1
E-health: a killer application for eletronic devices?
- Rudy Lauwereins:
Biomedical electronics serving as physical environmental and emotional watchdogs. 1-5 - Giovanni De Micheli, Cristina Boero, Camilla Baj-Rossi, Irene Taurino
, Sandro Carrara:
Integrated biosensors for personalized medicine. 6-11 - Wayne P. Burleson, Shane S. Clark, Benjamin Ransford, Kevin Fu:
Design challenges for secure implantable medical devices. 12-17
Design automation for things wet, small, spooky, and tamable
- Yan Luo, Krishnendu Chakrabarty:
Design of pin-constrained general-purpose digital microfluidic biochips. 18-25 - Daniel T. Grissom, Philip Brisk:
Path scheduling on digital microfluidic biochips. 26-35 - Zahra Sasanian, Robert Wille, D. Michael Miller:
Realizing reversible circuits using a new class of quantum gates. 36-41 - Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli:
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors. 42-47
Be efficient: low-power design techniques
- Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien:
A semiempirical model for wakeup time estimation in power-gated logic clusters. 48-55 - Hamid Reza Ghasemi, Abhishek A. Sinkar, Michael J. Schulte, Nam Sung Kim:
Cost-effective power delivery to support per-core voltage domains for power-constrained processors. 56-61 - Eric Donkoh, Alicia Lowery, Emily Shriver:
A hybrid and adaptive model for predicting register file and SRAM power using a reference design. 62-67 - Azalia Mirhoseini, Miodrag Potkonjak, Farinaz Koushanfar:
Coding-based energy minimization for phase change memory. 68-76
Design and data security: is it even possible?
- Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi:
A code morphing methodology to automate power analysis countermeasures. 77-82 - Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Security analysis of logic obfuscation. 83-89 - Sheng Wei, Kai Li, Farinaz Koushanfar, Miodrag Potkonjak:
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry. 90-95 - Domenic Forte, Ankur Srivastava:
On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction. 96-105
System simulation: the need for speed!
- Zhenman Fang, Qinghao Min, Keyong Zhou, Yi Lu, Yibin Hu, Weihua Zhang, Haibo Chen, Jian Li, Binyu Zang:
Transformer: a functional-driven cycle-accurate multicore simulator. 106-114 - Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi:
SAGA: SystemC acceleration on GPU architectures. 115-120 - Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid:
Synchronization for hybrid MPSoC full-system simulation. 121-126 - Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay:
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. 127-132
Can EDA combat the rise of electronic counterfeiting?
- Farinaz Koushanfar, Saverio Fazzari, Carl McCants, William Bryson, Matthew Sale, Peilin Song, Miodrag Potkonjak:
Can EDA combat the rise of electronic counterfeiting? 133-138
Reliability: from atoms to 3-D
- Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao:
Physics matters: statistical aging prediction under trapping/detrapping. 139-144 - Xuchu Hu, Walter James Condley, Matthew R. Guthaus:
Library-aware resonant clock synthesis (LARCS). 145-150 - Abhishek, Farid N. Najm:
Incremental power grid verification. 151-156 - Xin Zhao, Michael Scheuermann, Sung Kyu Lim:
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs. 157-162
EDA for emerging applications at the kilometer, micron, and nanometer scales
- Deokwoo Jung, Andreas Savvides, Athanasios Bamis:
Tracking appliance usage information in residential settings using off-the-shelf low-frequency meters. 163-168 - Xiaorong Zhang, He Huang, Qing Yang:
Implementing an FPGA system for real-time intent recognition for prosthetic legs. 169-175 - Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Lawrence T. Pileggi:
Statistical design and optimization for adaptive post-silicon tuning of MEMS filters. 176-181 - G. Reza Chaji, Javid Jaffari:
Generic low-cost characterization of Vth and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays. 182-187
Facing dependability: system-level solutions and cybercar challenges
- Jia Huang, Kai Huang, Andreas Raabe, Christian Buckl, Alois C. Knoll:
Towards fault-tolerant embedded systems with imperfect fault detection. 188-196 - Ivan Ukhov, Min Bao, Petru Eles, Zebo Peng:
Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systems. 197-204 - Michael Eberl, Michael Glaß, Jürgen Teich, Ulrich Abelein:
Considering diagnosis functionality during automatic system-level design of automotive networks. 205-213 - Yi Wang, Luis Angel D. Bathen, Nikil D. Dutt, Zili Shao:
Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems. 214-219 - Farinaz Koushanfar, Ahmad-Reza Sadeghi, Hervé Seudie:
EDA for secure and dependable cybercars: challenges and opportunities. 220-228
Volatile or non-volatile? that's the question
- Xavier Jimenez, David Novo, Paolo Ienne:
Software controlled cell bit-density to improve NAND flash lifetime. 229-234 - Chundong Wang, Weng-Fai Wong:
Observational wear leveling: an efficient algorithm for flash memory management. 235-242 - Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das:
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. 243-252 - Jue Wang, Xiangyu Dong, Yuan Xie:
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches. 253-258
Self-aware and adaptive technologies: the future of computing systems?
- Henry Hoffmann, Jim Holt, George Kurian, Eric Lau, Martina Maggio, Jason E. Miller, Sabrina M. Neuman, Mahmut E. Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha P. Chandrakasan, Srinivas Devadas:
Self-aware computing in the Angstrom processor. 259-264 - Lamia Youseff, Nathan Beckmann, Harshad Kasture, Charles Gruenwald III, David Wentzlaff, Anant Agarwal:
The case for elastic operating system services in fos. 265-270 - Joshua S. Auerbach, David F. Bacon, Ioana Burcea, Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla:
A compiler and runtime for heterogeneous computing. 271-276 - Simone Campanoni, Timothy M. Jones, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks:
The HELIX project: overview and directions. 277-282
Why model? beacuse reality is complicated enough!
- Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao:
Exploring sub-20nm FinFET design with predictive technology models. 283-288 - Yang Zhang, Haotian Liu, Qing Wang, Neric Fong, Ngai Wong:
Fast nonlinear model order reduction via associated transforms of high-order volterra transfer functions. 289-294 - Yangfeng Su, Fan Yang, Xuan Zeng:
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits. 295-300 - Arie Meir, Jaijeet S. Roychowdhury:
BLAST: efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric Lagrange enabled transient adjoint analysis. 301-310 - Aadithya V. Karthik, Jaijeet S. Roychowdhury:
DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics. 311-316 - Moongon Jung, David Z. Pan, Sung Kyu Lim:
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. 317-326
Is formal verification ready for the system level?
- Chun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, Chung-Yang (Ric) Huang:
Symbolic model checking on SystemC designs. 327-333 - Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
System verification of concurrent RTL modules by compositional path predicate abstraction. 334-343 - Kecheng Hao, Sandip Ray, Fei Xie:
Equivalence checking for behaviorally synthesized pipelines. 344-349 - Mitra Purandare, Kubilay Atasu, Christoph Hagleitner:
Proving correctness of regular expression accelerators. 350-355 - Sanjit A. Seshia:
Sciduction: combining induction, deduction, and structure for verification and synthesis. 356-365
NoCs next top model: from system-level to prototype
- Sahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot:
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces. 366-375 - Yoshi Shih-Chieh Huang, Yu-Chi Chang, Tsung-Chan Tsai, Yuan-Ying Chang, Chung-Ta King:
Attackboard: a novel dependency-aware traffic generator for exploring NoC design space. 376-381 - Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy:
Towards graceful aging degradation in NoCs through an adaptive routing algorithm. 382-391 - Andrew B. Kahng, Bill Lin, Siddhartha Nath:
Explicit modeling of control and data for improved NoC router estimation. 392-397 - Sunghyun Park, Tushar Krishna, Chia-Hsin Owen Chen, Bhavya K. Daya, Anantha P. Chandrakasan, Li-Shiuan Peh:
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI. 398-405 - Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. 406-411
Timing analysis and software-controlled memory: are we safe?
- Huping Ding, Yun Liang, Tulika Mitra:
WCET-centric partial instruction cache locking. 412-420 - Daniel Lo, G. Edward Suh:
Worst-case execution time analysis for parallel run-time monitoring. 421-429 - Kai Huang, Gang Chen, Christian Buckl, Alois C. Knoll:
Conforming the runtime inputs for hard real-time embedded systems. 430-436 - Mohammed El-Shambakey, Binoy Ravindran:
STM concurrency control for embedded real-time software with tighter time bounds. 437-446 - Luis Angel D. Bathen, Nikil D. Dutt:
HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories. 447-452 - Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang:
Age-based PCM wear leveling with nearly zero search cost. 453-458
Routing-driven design closure
- Michael Gester, Dirk Müller, Tim Nieberg, Christian Panten, Christian Schulte, Jens Vygen:
Algorithms and data structures for fast and good VLSI routing. 459-464 - Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou:
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. 465-470 - Gyuszi Suto:
Rule agnostic routing by using design fabrics. 471-475
Storing, computing, and storing while computing: the new face of non-volatility in systems
- Aaron Dingler, Steve Kurtz, Michael T. Niemier, Xiaobo Sharon Hu, György Csaba, Joseph Nahas, Wolfgang Porod, Gary H. Bernstein, Peng Li, Vjiay Karthik Sankar:
Making non-volatile nanomagnet logic non-volatile. 476-485 - Daniel Morris, David M. Bromberg, Jian-Gang Jimmy Zhu, Larry T. Pileggi:
mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices. 486-491 - Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy:
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture. 492-497 - Miao Hu, Hai Li, Qing Wu, Garrett S. Rose:
Hardware realization of BSB recall function using memristor crossbar arrays. 498-503
You can count on me: why it's OK to be imprecise or unreliable
- Jiawei Huang, John C. Lach, Gabriel Robins:
A methodology for energy-quality tradeoff using imprecise hardware. 504-509 - Georgios Karakonstantis, Christoph Roth, Christian Benkeser, Andreas Burg:
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon. 510-515 - Xue Lin, Yanzhi Wang, Siyu Yue, Donghwa Shin, Naehyuck Chang, Massoud Pedram:
Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effects. 516-521 - Younghyun Kim, Sangyoung Park, Naehyuck Chang, Qing Xie, Yanzhi Wang, Massoud Pedram:
Networked architecture for hybrid electrical energy storage systems. 522-528
Optimization to the rescue of analog
- Jin Sun, Priyank Gupta, Janet Meiling Wang Roveda:
A new uncertainty budgeting based method for robust analog/mixed-signal design. 529-535 - Seobin Jung, Yunju Choi, Jaeha Kim:
Variability-aware, discrete optimization for analog circuits. 536-541 - Bo Liu, Hadi Aliakbarian, Soheil Radiom, Guy A. E. Vandenbosch, Georges G. E. Gielen:
Efficient multi-objective synthesis for microwave components based on computational intelligence techniques. 542-548 - Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang:
Non-uniform multilevel analog routing with matching constraints. 549-554
Xterminating bugs
- Feng Yuan, Xiao Liu, Qiang Xu:
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug. 555-560 - David Lin, Ted Hong, Farzan Fallah, Nagib Hakim, Subhasish Mitra:
Quick detection of difficult bugs for effective post-silicon validation. 561-566 - Hongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, Ronald D. Blanton:
Test-data volume optimization for diagnosis. 567-572 - Xiaofei Guo, Ramesh Karri:
Invariance-based concurrent error detection for advanced encryption standard. 573-578
Brain-inspired autonomous computing and modeling
- Ahmed Al-Maashri, Michael DeBole, Matthew Cotter, Nandhini Chandramoorthy, Yang Xiao, Vijaykrishnan Narayanan, Chaitali Chakrabarti:
Accelerating neuromorphic vision algorithms for recognition. 579-584 - Robinson E. Pino, Hai (Helen) Li, Yiran Chen, Miao Hu, Beiye Liu:
Statistical memristor modeling and case study in neuromorphic computing. 585-590
Design, the next generation: from routing to capturing design expertise
- Qiang Ma, Hongbo Zhang, Martin D. F. Wong:
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. 591-596 - Yanheng Zhang, Chris Chu:
GDRouter: interleaved global routing and detailed routing for ultimate routability. 597-602 - Nikolai Ryzhenko, Steven M. Burns:
Standard cell routing via boolean satisfiability. 603-612 - Chih-Hung Liu, I-Che Chen, D. T. Lee:
An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction. 613-622 - Ofer Shacham, Sameh Galal, Sabarish Sankaranarayanan, Megan Wachs, John S. Brunhaver, Artem Vassiliev, Mark Horowitz, Andrew Danowitz, Wajahat Qadeer, Stephen Richardson:
Avoiding game over: bringing design to the next level. 623-629
Staying cool: modeling thermal effects in 3-D and multicore
- Seungwook Paek, Seok-Hwan Moon, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim:
PowerField: a transient temperature-to-power technique based on Markov random field theory. 630-635 - Juri Ranieri, Alessandro Vincenzi, Amina Chebira, David Atienza, Martin Vetterli:
EigenMaps: algorithms for optimal thermal maps extraction and sensor placement on multicore processors. 636-641 - Huapeng Zhou, Xin Li, Chen-Yong Cher, Eren Kursun, Haifeng Qian, Shi-Chune Yao:
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring. 642-647 - Jie Meng, Katsutoshi Kawakami, Ayse K. Coskun:
Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints. 648-655
SOS: specification, optimization, and synthesis in system-level design
- Arkadeb Ghosal, Rhishikesh Limaye, Kaushik Ravindran, Stavros Tripakis, Ankita Prasad, Guoqiang Wang, Trung N. Tran, Hugo A. Andrade:
Static dataflow with access patterns: semantics and analysis. 656-663 - Junchul Choi, Hyunok Oh, Sungchan Kim, Soonhoi Ha:
Executing synchronous dataflow graphs on a SPM-based multicore architecture. 664-671 - Glenn Leary, Weijia Che, Karam S. Chatha:
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. 672-677 - Akbar Sharifi, Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin:
Courteous cache sharing: being nice to others in capacity management. 678-687
Future of IC reliability
- Pratyush Kumar, Dip Goswami, Samarjit Chakraborty, Anuradha Annaswamy, Kai Lampka, Lothar Thiele:
A hybrid approach to cyber-physical systems verification. 688-696 - Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren D. Patel, Mahesh V. Tripunitara, Siddharth Garg:
Reliable computing with ultra-reduced instruction set co-processors. 697-702 - Xuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor:
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor. 703-708 - Hamid Shojaei, Azadeh Davoodi, Parmeswaran Ramanathan:
Confidentiality preserving integer programming for global routing. 709-716
Breaking out of EDA: how to apply EDA techniques to broader applications
- Louis Scheffer:
Design tools for artificial nervous systems. 717-722 - Frank Liu, Ben R. Hodges:
Dynamic river network simulation at large scale. 723-728 - Valeria Bertacco:
Humans for EDA and EDA for humans. 729-733 - Pey-Chang Kent Lin, Sunil P. Khatri:
Application of logic synthesis to the understanding and cure of genetic diseases. 734-740
The right placement at the right timing
- Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim:
Exploiting die-to-die thermal coupling in 3D IC placement. 741-746 - Myung-Chul Kim, Igor L. Markov:
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement. 747-752 - Samuel I. Ward, Duo Ding, David Z. Pan:
PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning. 756-761 - Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang:
Structure-aware placement for datapath-intensive circuit designs. 762-767 - Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
GLARE: global and local wiring aware routability evaluation. 768-773 - Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
The DAC 2012 routability-driven placement contest and benchmark suite. 774-782
Global views of synthesis: broadening the scope
- Kyle Kelley, Megan Wachs, John P. Stevenson, Stephen Richardson, Mark Horowitz:
Removing overhead from high-level interfaces. 783-789 - Johnathan York, Derek Chiou:
On the asymptotic costs of multiplexer-based reconfigurability. 790-795 - Swagath Venkataramani, Amit Sabne, Vivek Joy Kozhikkottu, Kaushik Roy, Anand Raghunathan:
SALSA: systematic logic synthesis of approximate circuits. 796-801 - Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization using metal-configurable gate-array spare cells. 802-807 - Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan:
Early prediction of NBTI effects using RTL source code analysis. 808-813 - Tobias Welp, Smita Krishnaswamy, Andreas Kuehlmann:
Generalized SAT-sweeping for post-mapping optimization. 814-819
Adaptive computing: when, where, why, how?
- Andrew B. Kahng, Seokhyeong Kang:
Accuracy-configurable adder for approximate arithmetic designs. 820-825 - Vivek Joy Kozhikkottu, Sujit Dey, Anand Raghunathan:
Recovery-based design for variation-tolerant SoCs. 826-833 - Hui Zhao, Ohyoung Jang, Wei Ding, Yuanrui Zhang, Mahmut T. Kandemir, Mary Jane Irwin:
A hybrid NoC design for cache coherence optimization for chip multiprocessors. 834-842 - Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman:
Architecture support for accelerator-rich CMPs. 843-849 - Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nigel C. Paver:
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC. 850-855 - Filippo Sironi, Davide B. Bartolini, Simone Campanoni, Fabio Cancare, Henry Hoffmann, Donatella Sciuto, Marco D. Santambrogio:
Metronome: operating system level performance management via self-adaptive computing. 856-865
Yin and yang of memories: the power-performance trade-off
- Muhammad Shafique, Bruno Zatt, Fabio Leandro Walter, Sergio Bampi, Jörg Henkel:
Adaptive power management of on-chip video memory for multiview video coding. 866-875 - Guangfei Zhang, Huandong Wang, Xinke Chen, Shuai Huang, Peng Li:
Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiency. 876-881 - Po-Chun Huang, Yuan-Hao Chang, Tei-Wei Kuo:
Joint management of RAM and flash memory with access pattern considerations. 882-887 - Dongki Kim, Sungkwang Lee, Jaewoong Chung, Daehyun Kim, Dong Hyuk Woo, Sungjoo Yoo, Sunggu Lee:
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU. 888-896 - Youngsik Kim, Sungjoo Yoo, Sunggu Lee:
Write performance improvement by hiding R drift latency in phase-change RAM. 897-906 - Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang:
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors. 907-912
Probabilistic embedded computing
- Christoph M. Kirsch, Hannes Payer:
Incorrect systems: it's not the problem, it's the solution. 913-917 - Joseph Sloan, John Sartori, Rakesh Kumar:
On software design for stochastic processors. 918-923 - Krishna V. Palem, Lingamneni Avinash:
What to do about the end of Moore's law, probably! 924-929 - Martin C. Rinard:
Obtaining and reasoning about good enough software. 930-935
Simulation-based verification: new ways to harness the workhorse
- Kai-Hui Chang, Chris Browy:
Improving gate-level simulation accuracy when unknowns exist. 936-940 - Jan Malburg, Alexander Finder, Görschwin Fey:
Automated feature localization for hardware designs using coverage metrics. 941-946 - Brian Keng, Andreas G. Veneris:
Path directed abstraction and refinement in SAT-based design debugging. 947-954 - Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco:
Checking architectural outputs instruction-by-instruction on acceleration platforms. 955-961
Ultra-low power using subthreshold and nearthreshold operation
- Bo Liu, Maryam Ashouei, Jos Huisken, José Pineda de Gyvez:
Standard cell sizing for subthreshold operation. 962-967 - Mingoo Seok:
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits. 968-973 - Joseph Crop, Robert Pawlowski, Patrick Chiang:
Regaining throughput using completion detection for error-resilient, near-threshold logic. 974-979 - Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongjun Park, Chaitali Chakrabarti, Scott A. Mahlke, David T. Blaauw, Trevor N. Mudge:
Process variation in near-threshold wide SIMD architectures. 980-987
Top picks of run-time power management techiques
- Karthik Chandrasekar, Benny Akesson, Kees Goossens:
Run-time power-down strategies for real-time SDRAM memory controllers. 988-993 - Lionel Vincent, Philippe Maurine, Suzanne Lesecq, Edith Beigné:
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring. 994-999 - Xiang Chen, Jian Zheng, Yiran Chen, Mengying Zhao, Chun Jason Xue:
Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices. 1000-1005 - Jilong Kuang, Laxmi N. Bhuyan, Raymond Klefstad:
Traffic-aware power optimization for network applications on multicore servers. 1006-1011
The dark side of test
- Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin:
Alternate hammering test for application-specific DRAMs and an industrial case study. 1012-1017 - Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Goal-oriented stimulus generation for analog circuits. 1018-1023 - Fangming Ye, Krishnendu Chakrabarty:
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation. 1024-1030 - Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Small delay testing for TSVs in 3-D ICs. 1031-1036
Design challenges and EDA solutions for wireless sensor networks
- Yoonmyung Lee, Yejoong Kim, Dongmin Yoon, David T. Blaauw, Dennis Sylvester:
Circuit and system design guidelines for ultra-low power sensor nodes. 1037-1042 - Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza:
Design exploration of energy-performance trade-offs for wireless sensor networks. 1043-1048 - Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Jérôme Willemin, Christian Piguet:
Energy harvesting and power management for autonomous sensor nodes. 1049-1054
Surviving timing challenges in nanometer designs
- Yi-Ting Chung, Jie-Hong Roland Jiang:
Functional timing analysis made fast and general. 1055-1060 - Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran:
Timing analysis with nonseparable statistical and deterministic variations. 1061-1066 - Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov:
Reversible statistical max/min operation: concept and applications to timing. 1067-1073 - Sanghamitra Roy, Koushik Chakraborty:
Predicting timing violations through instruction-level path sensitization analysis. 1074-1081
Special delivery: challenges in packaging
- Hsu-Chieh Lee, Yao-Wen Chang:
A chip-package-board co-design methodology. 1082-1087 - Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen:
Obstacle-avoiding free-assignment routing for flip-chip designs. 1088-1093 - Fu-Wei Chen, TingTing Hwang:
Clock tree synthesis with methodology of re-use in 3D IC. 1094-1099 - Xiang Qiu, Malgorzata Marek-Sadowska:
Can pin access limit the footprint scaling? 1100-1106
Renovate analog and mixed-signal circuit simulations
- Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif:
Yield estimation via multi-cones. 1107-1112 - Chin-Cheng Kuo, Wei-Yi Hu, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng:
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits. 1113-1118 - Xueqian Zhao, Zhuo Feng:
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners. 1119-1124 - Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong Yang:
Sparse LU factorization for parallel circuit simulation on GPU. 1125-1130
Heterogenous platforms: challenges and opportunities
- Michael B. Taylor:
Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse. 1131-1136 - Diego Melpignano, Luca Benini, Eric Flamand, Bruno Jego, Thierry Lepley, Germain Haugou, Fabien Clermidy, Denis Dutoit:
Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications. 1137-1142 - Brian Jeff:
Big.LITTLE system architecture from ARM: saving power through heterogeneous multiprocessing and task context migration. 1143-1146
Hot chips running cool - energy efficient near-threshold computing and its barriers
- Nathaniel Ross Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Assessing the performance limits of parallelized near-threshold computing. 1147-1152 - Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
Near-threshold voltage (NTV) design: opportunities and challenges. 1153-1158 - Leland Chang, Wilfried Haensch:
Near-threshold operation for power-efficient computing?: it depends... 1159-1163 - Matt Severson, Kendrick Yuen, Yang Du:
Not so fast my friend: is near-threshold computing the answer for power reduction of wireless devices? 1164-1166
Yielding in an uncertain world
- Yen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, Charles C. Chiang:
Accurate process-hotspot detection using critical design rule extraction. 1167-1172 - Jing Guo, Fan Yang, Subarna Sinha, Charles C. Chiang, Xuan Zeng:
Improved tangent space based distance metric for accurate lithographic hotspot classification. 1173-1178 - Shao-Yun Fang, Yao-Wen Chang:
Simultaneous flare level and flare variation minimization with dummification in EUVL. 1179-1184 - Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen:
A novel layout decomposition algorithm for triple patterning lithography. 1185-1190 - Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie:
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. 1191-1196 - Joonho Kong, Sung Woo Chung:
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors. 1197-1206
High-level synthesis is not just about translation!
- Lars Middendorf, Christophe Bobda, Christian Haubelt:
Hardware synthesis of recursive functions through partial stream rewriting. 1207-1215 - Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic:
Chisel: constructing hardware in a Scala embedded language. 1216-1225 - Carven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, Sharad Malik:
Specification and synthesis of hardware checkpointing and rollback mechanisms. 1226-1232 - Jason Cong, Peng Zhang, Yi Zou:
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. 1233-1238 - Jason Cong, Bin Liu:
A metric for layout-friendly microarchitecture optimization in high-level synthesis. 1239-1244 - Marcela Zuluaga, Peter A. Milder, Markus Püschel:
Computer generation of streaming sorting networks. 1245-1253
Wild and crazy ideas
- Wenchao Li, Sanjit A. Seshia, Somesh Jha:
CrowdMine: towards crowdsourced human-assisted verification. 1254-1255 - Ian G. Harris:
Extracting design information from natural language specifications. 1256-1257 - Elkim Roa, Wu-Hsin Chen, Byunghoo Jung:
Material implication in CMOS: a new kind of logic. 1258-1259 - Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean satisfiability using noise based logic. 1260-1261 - Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Cognitive computing with spin-based neural networks. 1262-1263 - Antoine Joubert, Marc Duranton, Bilel Belhadj, Olivier Temam, Rodolphe Héliot:
Capacitance of TSVs in 3-D stacked chips a problem?: not for neuromorphic systems! 1264-1265
Optimizing embedded software for high performance and reliability
- Jerónimo Castrillón, Andreas Tretter, Rainer Leupers, Gerd Ascheid:
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. 1266-1271 - Weijia Che, Karam S. Chatha:
Unrolling and retiming of stream applications onto embedded multicore processors. 1272-1277 - Brad K. Donohoo, Chris Ohlsen, Sudeep Pasricha, Charles Anderson:
Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems. 1278-1283 - Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula:
EPIMap: using epimorphism to map applications on CGRAs. 1284-1291 - Semeen Rehman, Muhammad Shafique, Jörg Henkel:
Instruction scheduling for reliability-aware compilation. 1292-1300 - John Sartori, Rakesh Kumar:
Compiling for energy efficiency on timing speculative processors. 1301-1308
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