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ORCIDPACT 2012: Minneapolis, MN, USA
- Pen-Chung Yew, Sangyeun Cho, Luiz DeRose, David J. Lilja:
International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012. ACM 2012, ISBN 978-1-4503-1182-3
Keynote address
- Peter J. Ungaro:
The changing role of supercomputing. 1-2
Power
- Wim Heirman
, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout:
Power-aware multi-core simulation for early design stage hardware/software co-optimization. 3-12 - Kai Ma, Xiaorui Wang:
PGCapping: exploiting power gating for power capping and core lifetime balancing in CMPs. 13-22 - Cong Liu, Jian Li, Wei Huang, Juan Rubio, Evan Speight, Xiaozhu Lin:
Power-efficient time-sensitive mapping in heterogeneous systems. 23-32
Runtime
- Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil:
Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. 33-42 - Justin Talbot, Zachary DeVito, Pat Hanrahan:
Riposte: a trace-driven compiler and parallel VM for vector code in R. 43-52 - Scott Schneider, Martin Hirzel, Bugra Gedik, Kun-Lung Wu:
Auto-parallelizing stateful distributed streaming applications. 53-64
NoC
- Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das:
PEPON: performance-aware hierarchical power budgeting for NoC based multicores. 65-74 - Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge:
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. 75-86 - Lei Wang, Poornachandran Kumar, Ki Hwan Yum, Eun Jung Kim:
APCR: an adaptive physical channel regulator for on-chip interconnects. 87-96
Scheduling and runtime
- Ioana Burcea, Livio Soares, Andreas Moshovos:
Pointy: a hybrid pointer prefetcher for managed runtime systems. 97-106 - Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura:
Scalability-based manycore partitioning. 107-116 - Kshitij Sudan, Sadagopan Srinivasan, Rajeev Balasubramonian, Ravi R. Iyer:
Optimizing datacenter power with memory system levers for guaranteed quality-of-service. 117-126
Best papers
- Amy Wang, Matthew Gaudet, Peng Wu, José Nelson Amaral, Martin Ohmacht, Christopher Barton, Raúl Silvera, Maged M. Michael:
Evaluation of blue Gene/Q hardware support for transactional memories. 127-136 - Víctor Jiménez, Roberto Gioiosa, Francisco J. Cazorla, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell:
Making data prefetch smarter: adaptive prefetching on POWER7. 137-146 - Ashay Rane, James C. Browne:
Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics. 147-156
Keynote address
- Kathy Yelick:
Compiling to avoid communication. 157-158
Transactional memory
- Justin Emile Gottschlich, Maurice Herlihy, Gilles Pokam, Jeremy G. Siek:
Visualizing transactional memory. 159-170 - Luke Dalessandro, Michael L. Scott:
Sandboxing transactional memory. 171-180 - Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström:
Transactional prefetching: narrowing the window of contention in hardware transactional memory. 181-190
Debugging and error detection
- Jingweijia Tan, Xin Fu:
RISE: improving the streaming processors reliability against soft errors in gpgpus. 191-200 - Michelle L. Goodstein, Shimin Chen, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
Chrysalis analysis: incorporating synchronization arcs in dataflow-analysis-based parallel monitoring. 201-212 - Ignacio Laguna, Dong H. Ahn, Bronis R. de Supinski, Saurabh Bagchi, Todd Gamblin:
Probabilistic diagnosis of performance faults in large-scale parallel applications. 213-222
Keynote address
- William T. C. Kramer:
Top500 versus sustained performance: the top problems with the top500 list - and what to do about them. 223-230
Multicore and mMultithread
- Yong Li, Rami G. Melhem, Alex K. Jones:
Practically private: enabling high performance CMPs through compiler-assisted data classification. 231-240 - Alberto Ros, Stefanos Kaxiras:
Complexity-effective multicore coherence. 241-252 - Yongbing Huang, Zehan Cui, Licheng Chen, Wenli Zhang, Yungang Bao, Mingyu Chen:
HaLock: hardware-assisted lock contention detection in multithreaded applications. 253-262
Optimization
- Torsten Hoefler, Timo Schneider:
Runtime detection and optimization of collective communication patterns. 263-272 - Md. Kamruzzaman, Steven Swanson, Dean M. Tullsen:
Coalition threading: combining traditional andnon-traditional parallelism to maximize scalability. 273-282 - Yi Yang, Ping Xiang, Mike Mantor, Norm Rubin, Huiyang Zhou:
Shared memory multiplexing: a novel way to improve GPGPU throughput. 283-292
Memory system (I)
- Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney, Joseph Nuzman:
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches. 293-304 - Andreas Sandberg, David Black-Schaffer, Erik Hagersten:
Efficient techniques for predicting cache sharing and throughput. 305-314 - Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng:
Optimal bypass monitor for high performance last-level caches. 315-324
Hybrid systems
- Vijay Sathish, Michael J. Schulte, Nam Sung Kim:
Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads. 325-334 - Rafael Ubal, Byunghyun Jang, Perhaad Mistry, Dana Schaa, David R. Kaeli:
Multi2Sim: a simulation framework for CPU-GPU computing. 335-344 - Abdullah Gharaibeh, Lauro Beltrão Costa, Elizeu Santos-Neto, Matei Ripeanu:
A yoke of oxen and a thousand chickens for heavy lifting graph processing. 345-354
Memory system (II)
- Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Todd C. Mowry:
The evicted-address filter: a unified mechanism to address both cache pollution and thrashing. 355-366 - Lei Liu, Zehan Cui, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong Wu:
A software memory partition approach for eliminating bank-level interference in multicore systems. 367-376 - Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
Base-delta-immediate compression: practical data compression for on-chip caches. 377-388
Accelerators
- Anil Krishna, Timothy Heil, Nicholas Lindberg, Farnaz Toussi, Steven VanderWiel:
Hardware acceleration in the IBM PowerEN processor: architecture and performance. 389-400 - Hao Wang, Vijay Sathish, Ripudaman Singh, Michael J. Schulte, Nam Sung Kim:
Workload and power budget partitioning for single-chip heterogeneous processors. 401-410 - Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Balakrishna Iyer, Bernard Brezzo, Donna Dillenberger, Sameh W. Asaad:
Database analytics acceleration using FPGAs. 411-420
PACT poster papers
- Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo:
LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures. 421-422 - Jong-Hyuk Lee, Ziyi Liu, Xiaonan Tian, Dong Hyuk Woo, Weidong Shi, Dainis Boumber, Yonghong Yan, Kyeong-An Kwon:
Acceleration of bulk memory operations in a heterogeneous multicore architecture. 423-424 - Nilanjan Goswami, Zhongqi Li, Ajit Verma, Ramkumar Shankar, Tao Li:
Integrating nanophotonics in GPU microarchitecture. 425-426 - John Sartori, Rakesh Kumar:
Branch and data herding: reducing control and memory divergence for error-tolerant GPU applications. 427-428 - Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng:
Layout-oblivious optimization for matrix computations. 429-430 - Pierre Estérie, Mathias Gaunard, Joel Falcou, Jean-Thierry Lapresté, Brigitte Rozoy:
Boost.SIMD: generic programming for portable SIMDization. 431-432 - Zhijia Zhao, Bo Wu, Xipeng Shen:
Speculative parallelization needs rigor: probabilistic analysis for optimal speculation of finite-state machine applications. 433-434 - Vladimir Gajinov, Srdjan Stipic, Osman S. Unsal, Tim Harris, Eduard Ayguadé, Adrián Cristal:
Supporting stateful tasks in a dataflow graph. 435-436 - Alexander Collins, Christian Fensch, Hugh Leather:
MaSiF: machine learning guided auto-tuning of parallel skeletons. 437-438 - Lihang Zhao, Woojin Choi, Jeffrey T. Draper:
TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency. 439-440 - Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das:
Application-aware prefetch prioritization in on-chip networks. 441-442 - Jason Zebchuk, Harold W. Cain, Vijayalakshmi Srinivasan, Andreas Moshovos:
ReCaP: a region-based cure for the common cold cache. 443-444 - Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte:
Power-efficient computing for compute-intensive GPGPU applications. 445-446 - Wei Ding, Mahmut T. Kandemir, Yuanrui Zhang, Emre Kultursay:
Off-chip access localization for NoC-based multicores. 447-448 - Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou:
Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing. 449-450 - Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez, José Duato:
PS-Dir: a scalable two-level directory cache. 451-452 - Foivos S. Zakkak, Dimitrios Chasapis, Polyvios Pratikakis, Angelos Bilas, Dimitrios S. Nikolopoulos:
Inference and declaration of independence: impact on deterministic task parallelism. 453-454 - Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi:
Application-to-core mapping policies to reduce memory interference in multi-core systems. 455-456 - David Eklov, Nikos Nikoleris, David Black-Schaffer, Erik Hagersten:
Bandwidth bandit: quantitative characterization of memory contention. 457-458 - Rakesh Kumar, Alejandro Martínez, Antonio González:
Speculative dynamic vectorization for HW/SW co-designed processors. 459-460 - Bin Ren, Gagan Agrawal, James R. Larus, Todd Mytkowicz, Tomi Poutanen, Wolfram Schulte:
Fine-grained parallel traversals of irregular data structures. 461-462 - Aydin Buluç, Armando Fox, John R. Gilbert, Shoaib Kamil, Adam Lugowski, Leonid Oliker, Samuel Williams:
High-performance analysis of filtered semantic graphs. 463-464 - Karthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham:
Energy-efficient cache partitioning for future CMPs. 465-466 - Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas:
A low-overhead dynamic optimization framework for multicores. 467-468 - Congming Chen, Wei Huo, Xiaobing Feng:
Making it practical and effective: fast and precise may-happen-in-parallel analysis. 469-470
ACM SRC abstracts
- Woojin Choi, Lihang Zhao, Jeff Draper:
Mileage-based contention management in transactional memory. 471-472 - Shuaiwen Song, Kirk W. Cameron:
System-level power-performance efficiency modeling for emergent GPU architectures. 473-474 - Matthew Gaudet, José Nelson Amaral:
Transactional event profiling in a best-effort hardware transactional memory system. 475-476 - Hari K. Pyla, Srinidhi Varadarajan:
Transparent runtime deadlock elimination. 477-478 - Peng Li, Kevin Gomez, David J. Lilja:
Design of a storage processing unit. 479-480 - Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam:
SkipCache: miss-rate aware cache management. 481-482 - Arnamoy Bhattacharyya:
Using combined profiling to decide when thread level speculation is profitable. 483-484 - Biswabandan Panda, Shankar Balachandran:
Hardware prefetchers for emerging parallel applications. 485-486 - Fábio Coutinho, Luís Alfredo V. de Carvalho:
Strategies based on green policies to the grid resource allocation. 487-488 - Gennady Pekhimenko, Todd C. Mowry, Onur Mutlu:
Linearly compressed pages: a main memory compression framework with low complexity and low latency. 489-490 - Cong Liu:
Energy-efficient workload mapping in heterogeneous systems with multiple types of resources. 491-492 - Lina Sawalha, Ronald D. Barnes:
Phase-based scheduling and thread migration for heterogeneous multicore processors. 493-494
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