• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 107 matches

• 2016
• 
  Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, David T. Blaauw, Dennis Sylvester:
  A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm. VLSI Circuits 2016: 1-2
• 
  Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy:
  A 350mV-900mV 2.1GHz 0.011mm² regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2
• 
  Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor:
  A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. VLSI Circuits 2016: 1-2
• 
  Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken:
  A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um² 6T bitcell in a 16nm FinFET CMOS process. VLSI Circuits 2016: 1-2
• 
  Milovan Blagojevic, Martin Cochet, Ben Keller, Philippe Flatresse, Andrei Vladimirescu, Borivoje Nikolic:
  A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. VLSI Circuits 2016: 1-2
• 
  Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa:
  A microcontroller with 96% power-conversion efficiency using stacked voltage domains. VLSI Circuits 2016: 1-2
• 
  Ryan Boesch, Kevin Zheng, Boris Murmann:
  A 0.003 mm² 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE. VLSI Circuits 2016: 1-2
• 
  Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas:
  A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array. VLSI Circuits 2016: 1-2
• 
  Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn:
  A 16-channel noise-shaping machine learning analog-digital interface. VLSI Circuits 2016: 1-2
• 
  Chao Chen, Zhao Chen, Deep Bera, Shreyas B. Raghunathan, Maysam Shabanimotlagh, Emile Noothout, Zu-yao Chang, Jacco Ponte, Christian Prins, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs:
  A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography. VLSI Circuits 2016: 1-2
• 
  Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang:
  A 0.9um² 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. VLSI Circuits 2016: 1-2
• 
  Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang:
  Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers. VLSI Circuits 2016: 1-2
• 
  Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang:
  A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. VLSI Circuits 2016: 1-2
• 
  Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De:
  Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. VLSI Circuits 2016: 1-2
• 
  Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, Jaeha Kim:
  A field-programmable mixed-signal IC with time-domain configurable analog blocks. VLSI Circuits 2016: 1-2
• 
  Qing Dong, Kaiyuan Yang, David T. Blaauw, Dennis Sylvester:
  A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems. VLSI Circuits 2016: 1-2
• 
  Richard Dorrance, Dejan Markovic:
  A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT. VLSI Circuits 2016: 1-2
• 
  Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang:
  A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. VLSI Circuits 2016: 1-2
• 
  Matthias Eberlein, Idan Yahav:
  A 28nm CMOS ultra-compact thermal sensor in current-mode technique. VLSI Circuits 2016: 1-2
• 
  Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang:
  A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. VLSI Circuits 2016: 1-2
• 
  Jeffrey C. Gealow, Masato Motomura:
  Foreword. VLSI Circuits 2016: 1-2
• 
  Patrick R. Gill, Thomas Vogelsang:
  Lensless Smart Sensors: Optical and thermal sensing for the Internet of Things. VLSI Circuits 2016: 1-2
• 
  Yan Hong, Yong Wang, Wang Ling Goh, Yuan Gao, Lei Yao:
  A 9.84-73.2 nJ, 0.048 mm² time-domain impedance sensor that provides values of resistance and capacitance. VLSI Circuits 2016: 1-2
• 
  A. K. M. Delwar Hossain, Aurangozeb, Maruf Mohammad, Masum Hossain:
  A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS. VLSI Circuits 2016: 1-2
• 
  Sung-En Hsieh, Chih-Cheng Hsieh:
  A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC. VLSI Circuits 2016: 1-2
• 
  Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
  A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants. VLSI Circuits 2016: 1-2
• 
  Gunpil Hwang, JongKwan Choi, Jaehyeok Yang, Sungmin Lim, Jae-Myoung Kim, MinGyu Choi, Dae-Shik Kim, Kiuk Gwak, Jinwoo Jeon, Hee Sup Shin, Il-Hwan Choi, Sol Park, Hyeon-Min Bae:
  A 2.048 Mb/s full-duplex free-space optical transceiver IC for a real-time in vivo neurofeedback mouse experiment under social interaction. VLSI Circuits 2016: 1-2
• 
  Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim:
  A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. VLSI Circuits 2016: 1-2
• 
  Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu:
  An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. VLSI Circuits 2016: 1-2
• 
  Ankesh Jain, Shanthi Pavan:
  A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. VLSI Circuits 2016: 1-2

skipping 77 more matches