"A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic ..."

Haonan Zhu et al. (2024)

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DOI: 10.1109/TCSI.2024.3395442

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type: Journal Article

metadata version: 2024-07-19

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Haonan Zhu, Bi Wu, Tianyang Yu, Ke Chen, Chenggang Yan, Weiqiang Liu:
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3165-3178 (2024)

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