"High-Speed Area-Efficient Multiplier Design Using Multiple-Valued ..."

Shoji Kawahito et al. (1994)

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DOI: 10.1109/12.250607

access: closed

type: Journal Article

metadata version: 2017-05-20

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Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994)

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