"A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC."

Jun Terada et al. (2008)

> Home

Details and statistics

DOI: 10.1109/JSSC.2008.2006229

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/TeradaNKKYO08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/TeradaNKKYO08
Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo:
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC. IEEE J. Solid State Circuits 43(12): 2921-2928 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.