default search action
"VHDL generation from a timed extension of the formal description technique ..."
Carlos Delgado Kloos et al. (1993)
- Carlos Delgado Kloos, Tomás Pedro de Miguel Moro, Tomás Robles Valladares, Guadalberto Rabay Filho, Andrés Marín López:
VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project. Microprocess. Microprogramming 38(1-5): 589-596 (1993)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.