"Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering ..."

George Kurian et al. (2009)

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DOI: 10.1166/JOLPE.2009.1001

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type: Journal Article

metadata version: 2020-09-10

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George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi:
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. 5(1): 58-68 (2009)

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