"A Novel Power-Managed Scan Architecture for Test Power and Test Time ..."

V. R. Devanathan et al. (2008)

> Home

Details and statistics

DOI: 10.1166/JOLPE.2008.150

access: closed

type: Journal Article

metadata version: 2020-09-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jolpe/DevanathanRMK08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jolpe/DevanathanRMK08
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4(1): 101-110 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.