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"Selective Trigger Scan Architecture for Reducing Power, Time and Data ..."
Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi (2003)
- Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi:
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220
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