"Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated ..."

Gaurang Upasani et al. (2009)

> Home

Details and statistics

DOI: 10.1007/978-3-642-11802-9_27

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/patmos/UpasaniCMMP09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/patmos/UpasaniCMMP09
Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. PATMOS 2009: 227-236

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.