"18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test ..."

Kyomin Sohn et al. (2016)

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DOI: 10.1109/ISSCC.2016.7418034

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin:
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. ISSCC 2016: 316-317

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